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Temperature-Dependent Soft-Error Analysis from 300K to 77K in Nanosheet and CFET

Temperature-Dependent Soft-Error Analysis from 300K to 77K in Nanosheet and CFET 150 150
Author(s): Sufia Shahin, Hafeez Raza, Avinash Lahgere, Yogesh Singh Chauhan, Hussam Amrouch

Abstract:

We investigate the impact of cryogenic temperatures on the Single Event Upset (SEU) reliability of the Gate-All-Around (GAA) Nanosheet FET (NSFET) and Complementary FET (CFET) devices. At the device level, we assess heavy-ion radiation (HIR)-induced transients and carrier profiles and compare CFET and NSFET at temperatures from 400K to 77 …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3740550
Publisher: IEEE

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Sensing- and Periphery-Aware Modeling of a Hybrid MTJ–CMOS Nonvolatile 1-bit Sign-Weight Memory Subsystem for Energy-Constrained Edge Inference

Sensing- and Periphery-Aware Modeling of a Hybrid MTJ–CMOS Nonvolatile 1-bit Sign-Weight Memory Subsystem for Energy-Constrained Edge Inference 150 150
Author(s): Byeong-Gwon Kim, Byeong-Kwon Ju, Ki-Young Lee

Abstract:

The spin-transfer-torque magnetic random access memory (STT-MRAM) is attractive for nonvolatile 1-bit sign-weight storage, but a favorable cell or local-read metric does not establish subsystem efficiency. We analyze a hybrid magnetic tunnel junction (MTJ)–complementary metal–oxide–semiconductor (CMOS) memory subsystem, in which MTJs store static signs while sensing, reference …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 192 – 198
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3726699
Publisher: IEEE

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SEAL: Multitenant Security-Aware Layer Mapping for Heterogeneous 3-D CiM Accelerators

SEAL: Multitenant Security-Aware Layer Mapping for Heterogeneous 3-D CiM Accelerators 150 150
Author(s): Pragya Sharma, Sriniketh Purisai Ramanujam, Ashish Reddy Bommana, Hossein Pourmehrani, Naghmeh Karimi, Farshad Firouzi, Krishnendu Chakrabarty

Abstract:

Heterogeneous 3-D compute-in-memory (CiM) architectures have emerged as an efficient acceleration paradigm for deep neural network (DNN) inference by leveraging the complementary characteristics of diverse memory technologies enabled through 3-D integration. Prior work has focused on architectural efficiency and workload-mapping optimization, leaving the security implications of heterogeneous CiM systems largely …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 205 – 213
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3734047
Publisher: IEEE

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DTCO of NOR-Type IGZO FeFETs for 3D Heterogeneous AI Memories: A Read-Centric Perspective

DTCO of NOR-Type IGZO FeFETs for 3D Heterogeneous AI Memories: A Read-Centric Perspective 150 150
Author(s): Yang Xiang, Zhuo Chen, Nicolò Ronchi, Arvind Sharma, Fernando García-Redondo, Subhali Subhechha, Attilio Belmonte, Maarten Rosmeulen, Gouri Sankar Kar, Dwaipayan Biswas, Jan Van Houdt

Abstract:

InGaZnO (IGZO)-channel FeFETs have attracted notable interest thanks to recent advances in endurance, opening up their application space for read-dominated AI memory tiers. This work evaluates the viability of NOR-type IGZO FeFETs for 3D heterogeneous AI memories from a read-centric design-technology cooptimization (DTCO) perspective, spanning on-chip back-end-of-line (BEOL) RAMs …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3740054
Publisher: IEEE

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Insights into the S-Curve Engineering in Ferroelectric-on-Top Negative-Capacitance CFET for Ultra-Low Power Computing

Insights into the S-Curve Engineering in Ferroelectric-on-Top Negative-Capacitance CFET for Ultra-Low Power Computing 150 150
Author(s): Sandeep Semwal, Pin Su

Abstract:

The growing demand for energy-efficient computing has intensified interest in highly scalable device technologies such as complementary field-effect transistors (CFETs). In this work, we investigate S-curve engineering for a unique ferroelectric-on-top (FE-o-T) negative-capacitance (NC) CFET through calibrated numerical simulations to assess its potential for ultra-low-power computing and supply-voltage scaling. Our …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3740342
Publisher: IEEE

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A Hybrid-Bonded 12.1 TOPS/mm2 56-Core DNN Processor With 2.5 Tb/s/mm2 3D Network on Chip in Intel 18A and Intel 3

A Hybrid-Bonded 12.1 TOPS/mm2 56-Core DNN Processor With 2.5 Tb/s/mm2 3D Network on Chip in Intel 18A and Intel 3 150 150
Author(s): Phil C. Knag, Gregory K. Chen, Shanshan Xie, Satish Yada, Wei Wu, Yu-Shiang Lin, Alexander Kashirin, Xiemei Meng, Russell Criss, Ana Sonia Leon, Carlos Tokunaga, Ram K. Krishnamurthy, James W. Tschanz

Abstract:

This article presents a modular 3D stacked manycore processor that integrates a general-purpose RISC-V base die with a domain-specific deep neural network (DNN) accelerator die using a 9 $\mu $ m hybrid-bonded interconnect (HBI). A custom $14 \times 4~\times 2$ 3D network-on-chip (3D NoC) provides a flat, distributed shared-memory address space across 112 tiles, enabling …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3735250
Publisher: IEEE

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Open DRAM Model—Part II: Enabling Processing-in-Memory in 3-D DRAM

Open DRAM Model—Part II: Enabling Processing-in-Memory in 3-D DRAM 150 150
Author(s): Kiseok Lee, Seongkwang Lim, Suman Datta, Shimeng Yu

Abstract:

Processing-in-memory (PIM) by implementing Boolean logic functions in dynamic random access memory (DRAM) has been proposed to alleviate the memory wall problem in data-intensive computing. However, quantitatively evaluating DRAM-based logic operations across different DRAM architectures remains challenging due to the lack of publicly available DRAM cell and peripheral transistor models …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 144 – 152
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3704508
Publisher: IEEE

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A 6-bit Serializer With Integrated Manchester Encoder Using Flexible a-IGZO TFT Technology

A 6-bit Serializer With Integrated Manchester Encoder Using Flexible a-IGZO TFT Technology 150 150
Author(s): Suyash Shrivastava, Pydi Ganga Bahubalindruni

Abstract:

This article presents an experimental characterization of a novel 6-bit parallel-to-serial data converter integrated with a Manchester encoder. The system comprises an on-chip digital logic block that generates six mutually nonoverlapping control signals ( $\phi _{0-5}$ ) and three 120° phase-shifted clock signals to drive the switching transistors in the serializer and the …

Published in: IEEE Solid-State Circuits Letters
Page(s): 194 – 197
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3707465
Publisher: IEEE

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An Extendable Wideband Band-Divided SPnT Switch Topology Based on a Reconfigurable Pole-to-Throw Network

An Extendable Wideband Band-Divided SPnT Switch Topology Based on a Reconfigurable Pole-to-Throw Network 150 150
Author(s): Zhaowu Wang, Hao Ning, Xinyan Li, Ze Yu, Qiliang Li, Xiaochen Tang, Yong Wang

Abstract:

This article presents an extendable wideband band-divided SP $n$ T switch topology based on a reconfigurable pole-to-throw network (RPTN). Compared to conventions, it mitigates the loss degradation resulting from complex signal routing in advanced RF front-ends. This is enabled by the RPTN, which divides the throws into low-/mid-/high-band (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3711644
Publisher: IEEE

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