Silicon-on-insulator

1-Transistor-Dynamic Random Access Memory as Reservoir for Temporal Signal Processing

1-Transistor-Dynamic Random Access Memory as Reservoir for Temporal Signal Processing 150 150

Abstract:

Reservoir computing (RC), a computational paradigm inspired by the recurrent neural networks (RNNs), offers a promising framework for efficient temporal processing with minimal training overhead. Hardware implementation of RC primitive requires devices that exhibit short-term memory, nonlinearity, and energy-efficient state-switching dynamics. While emerging nonvolatile memory (eNVM) technologies have been explored …

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The Impact of Magnetic Field on Defective FDSOI and FinFET Devices

The Impact of Magnetic Field on Defective FDSOI and FinFET Devices 150 150

Abstract:

This article explores the efficacy of a unique defect detection mechanism for the FinFET and FDSOI transistors: magnetomodulation of drain current. Using multiphysics technology CAD (TCAD), we model the impact of static and transient magnetic fields on drain current in the following defect-free and defective devices: 1) FDSOI with interface trap …

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A W-Band Active Bidirectional Phase Shifter With 2° RMS Phase Error Over 26.4% FBW Using Back-Gate Biasing in 28-nm FD-SOI CMOS

A W-Band Active Bidirectional Phase Shifter With 2° RMS Phase Error Over 26.4% FBW Using Back-Gate Biasing in 28-nm FD-SOI CMOS 150 150

Abstract:

This article presents a W-band active bidirectional vector-sum phase shifter (Bi-VSPS) using a bidirectional phase-inverting variable-gain amplifier (Bi-PIVGA) with back-gate biasing in 28-nm fully depleted silicon-on-insulator (FD-SOI) CMOS. The Bi-PIVGA employs a neutralization technique that cancels the gate-to-drain capacitances of both active and inactive transistors in each signal direction. By …

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High-Precision Close-to-Analog Programming of PCM Cells as Devices for AiMC Edge-AI

High-Precision Close-to-Analog Programming of PCM Cells as Devices for AiMC Edge-AI 150 150

Abstract:

This article presents a high-precision close-to-analog programming methodology for phase-change memory (PCM) cells, targeting analog in-memory computing (AiMC) architectures for edge-artificial intelligence (AI) applications. By leveraging an iterative accumulation approach during the verify phase, the proposed technique enhances the effective number of bits (ENOBs) achievable in PCM cells. Experimental validation …

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Adaptive Linearity Enhancement of Low-Noise Amplifiers Using Doherty Active Load Modulation

Adaptive Linearity Enhancement of Low-Noise Amplifiers Using Doherty Active Load Modulation 150 150

Abstract:

This article introduces Doherty active load modulation into low-noise amplifier (LNA) designs to dynamically enhance linearity. Under nominal small-signal conditions, the proposed LNA operates like conventional counterparts, consuming no additional power. When strong in-band blockers are present, auxiliary paths are adaptively engaged to activate a high-linearity mode without incurring a …

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On-Chip Charge-Trap-Transistor-Based Mismatch Calibration of an 8-Bit Thermometer Current-Source DAC

On-Chip Charge-Trap-Transistor-Based Mismatch Calibration of an 8-Bit Thermometer Current-Source DAC 150 150

Abstract:

This letter presents an on-chip mismatch calibration technique for current-source digital-to-analog converters (DACs) using charge-trap transistors (CTTs) in 22-nm FDSOI technology. The proposed method exploits programmable threshold voltage (VTH) shifts in CTTs to locally tune the current of near-minimum-sized devices without external trimming. A compact 8-bit thermometer DAC is implemented …

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Dual-Junction Monolithically Integrated Monitoring Photodiode With a Two-Stage 18 GHz 18 pA/√Hz TIA in 22-nm FDSOI

Dual-Junction Monolithically Integrated Monitoring Photodiode With a Two-Stage 18 GHz 18 pA/√Hz TIA in 22-nm FDSOI 150 150

Abstract:

We present a monolithically integrated (MI) dualjunction monitoring photodiode (PD) and transimpedance amplifier (TIA). The photocurrent originates from the deep Nwell (DNW)/P-type substrate (PSUB) $({\lt }5~ \mathrm {GHz})$ and the P-Well $(\mathrm {PW}) / \mathrm {DNW}({\gt }1~ \mathrm {GHz})$ junctions. The presented combination of bulk PD and 22 nm fully-depleted silicon-on-insulator (FDSOI) …

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