Signal to noise ratio

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A Hybrid Touch Sensing AFE With Common-CVQ (Currents, Voltages, and Charges) Subtraction to Improve Display Noise Immunity for Large Sensing Load

A Hybrid Touch Sensing AFE With Common-CVQ (Currents, Voltages, and Charges) Subtraction to Improve Display Noise Immunity for Large Sensing Load 150 150
Author(s): Seung Hun Choi, Jun Yeol An, Jaewoong Ahn, Si-Woo Kim, Jae-Youl Lee, Yoon-Kyung Choi, Hyung-Min Lee

Abstract:

On-cell touch flexible organic light-emitting diode (OLED) displays face significant display noise (D-noise) challenges due to large parasitic capacitance ( $C_{P}$ ). To address the limitations of conventional methods, this article proposes improved common-current subtraction (CCS), incorporating common-voltage subtraction (CVS) and common-charge subtraction (CQS) techniques. CVS enhances signal-to-noise ratio (SNR) by …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3675678
Publisher: IEEE

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A 0.5–2.5-GS/s Resettable Ring-VCO-Based ADC Eliminating Quantization-Noise Shaping

A 0.5–2.5-GS/s Resettable Ring-VCO-Based ADC Eliminating Quantization-Noise Shaping 150 150
Author(s): Tao Lu, Zixiang Liu, Hao Yang, Sai-Weng Sin, Fujiang Lin, Liheng Lou, Robert Bogdan Staszewski, Yizhe Hu

Abstract:

This article presents a Nyquist-rate Analog-to-digital converter (ADC) operating from 0.5 to 2.5 GS/s based on an open-loop resettable ring VCO (R-RVCO). By inherently embedding the $1 {\,}-{\,}z^{-1}$ transfer function, the R-RVCO eliminates the need for an explicit differentiator, suppresses VCO phase-noise (PN) integration, and avoids quantization-noise (QN) shaping within …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3668599
Publisher: IEEE

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An Optimal Modulation Bits-to-RF Digital Transmitter Using Time-Interleaved Multi-Subharmonic Switching

An Optimal Modulation Bits-to-RF Digital Transmitter Using Time-Interleaved Multi-Subharmonic Switching 150 150
Author(s): Timur Zirtiloglu, Arman Tan, Basak Ozaydin, Ken R. Duffy, Muriel Médard, Rabia Tugce Yazicigil

Abstract:

This article presents a fully integrated bits-to-RF transmitter (Tx) featuring deep power back-off (PBO) enhancements, leveraging a multi-subharmonic switching (multi-SHS) digital power amplifier (DPA) with time-interleaving and a harmonic-rejection digital-to-phase converter (DPC). This work employs a nonuniform optimal modulation (OM) constellation, where symbol probability is inversely related to its amplitude, …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3659903
Publisher: IEEE

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A 475-nW Area-Efficient Programmable Analog Feature Extraction Filterbank for Audio Classification

A 475-nW Area-Efficient Programmable Analog Feature Extraction Filterbank for Audio Classification 150 150
Author(s): Patrice Abbie D. Legaspi, Shubham Yadav, Mark S. Oude Alink, Bram Nauta

Abstract:

Audio classification in edge devices has many applications and can be implemented at varying levels of complexity, typically consisting of a feature extractor followed by a classifier. Such devices are often always-on, constantly listening to their surroundings, and have a small form factor; therefore, they require low-power operation and high …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3655426
Publisher: IEEE

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A Folded-Differential Switched-Capacitor SRAM CIM Macro With Scalable MAC Sizes for TinyML Inference

A Folded-Differential Switched-Capacitor SRAM CIM Macro With Scalable MAC Sizes for TinyML Inference 150 150
Author(s): Zhonghao Chen, Ling-An Cheong, Tianyi Yu, Yiming Chen, Guodong Yin, Teng Yi, Yongpan Liu, Huazhong Yang, Xueqing Li

Abstract:

This letter presents a switched-capacitor SRAM compute-in-memory macro optimized for TinyML inference. Key features include: 1) an area-efficient folded-differential multiply-and-accumulate (FD-MAC) scheme to double the signal margin; 2) a closed-loop floating-inverter amplifier (FIA)-based charge accumulation technique for signal-to-noise ratio enhancement and multiply-and-accumulate (MAC) voltage integration; and 3) a sparsity-aware multistep MAC method …

Published in: IEEE Solid-State Circuits Letters
Page(s): 73 – 76
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3662477
Publisher: IEEE

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A 24.5–45.2-GHz Low-Jitter Compact Differentially Injection-Locked Clock Multiplier With Folded-Inductor-Based Magnetic-Flux Cancellation

A 24.5–45.2-GHz Low-Jitter Compact Differentially Injection-Locked Clock Multiplier With Folded-Inductor-Based Magnetic-Flux Cancellation 150 150
Author(s): Feifan Hong, Jiawen Chen, Pingda Guan, Sayan Kumar, Robert Bogdan Staszewski, Teerachot Siriburanon

Abstract:

In this article, we present a differentially injection-locked clock multiplier (ILCM) featuring an ultra-wide frequency tuning range (TR) and low jitter, achieved through a compact folded-inductor-based magnetic-flux cancellation technique. A co-designed series-LC dual-mode quadrature ring oscillator (QRO) and edge-combining frequency doubler operating in the mm-wave band jointly extend the TR …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1410 – 1424
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3640957
Publisher: IEEE

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A 129–146-GHz Direct-Digital Modulation FinFET Transmitter With On-Chip Mismatch Calibrations for Beyond-5G Wireless Communications

A 129–146-GHz Direct-Digital Modulation FinFET Transmitter With On-Chip Mismatch Calibrations for Beyond-5G Wireless Communications 150 150
Author(s): Runzhou Chen, Hao-Yu Chien, Boxun Yan, Chao-Jen Tien, Mau-Chung Frank Chang

Abstract:

This article presents a D-band direct-digital modulation (DDM) transmitter with on-chip digital calibration blocks for future beyond-5G (B5G) wireless communication. The proposed DDM architecture mitigates the need for complex intermediate frequency (IF) generation and power-hungry digital-to-analog converters (DACs). The transmitter is implemented primarily in TSMC’s 16-nm p-FinFETs, …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1776 – 1790
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3644224
Publisher: IEEE

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A 112-Gb/s PAM4 Receiver With a Phase Equalization AFE in 7-nm FinFET

A 112-Gb/s PAM4 Receiver With a Phase Equalization AFE in 7-nm FinFET 150 150
Author(s): Huanan Guo, Yufeng Yao, Xiang Gao

Abstract:

To reduce the bit-error-rate (BER), equalizers are implemented in high-speed SerDes receivers (RX) to compensate for channel insertion loss and mitigate intersymbol interference (ISI). Conventional analog front-end (AFE) designs primarily focus on amplitude gain while neglecting the influence of phase shift. This brief presents a phase equalization (PEQ) AFE design …

Published in: IEEE Solid-State Circuits Letters
Page(s): 5 – 8
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3637833
Publisher: IEEE

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A “No Gain” Direct-Conversion IQ RF-to-Bits Receiver Without Active Linear Amplification

A “No Gain” Direct-Conversion IQ RF-to-Bits Receiver Without Active Linear Amplification 150 150
Author(s): Jeroen Ponte, Roel Plompen, Emiel Zijlma, Eric A. M. Klumperink, Harijot Singh Bindra, Bram Nauta

Abstract:

This work describes a direct-conversion IQ receiver (RX) that does not utilize any active linear (power) amplification, covering its design considerations, prototype implementation, and measurement verification. Only RLC components, MOS transistor (MOST) switches, and comparators are used, leading to several unique design challenges. Key among these are the fact that …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 17
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3611114
Publisher: IEEE

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