A Wide-Lock-in-Range and Fast-Settling-Time, 11.6-to-14-GHz SSPLL With an Event-Driven FLL and a Low-Power Harmonic-Lock Detector https://sscs.ieee.org/wp-content/themes/movedo/images/empty/thumbnail.jpg 150 150 https://secure.gravatar.com/avatar/8fcdccb598784519a6037b6f80b02dee03caa773fc8d223c13bfce179d70f915?s=96&d=mm&r=g
Abstract:
This article presents a wide-lock-in-range and fast-settling-time, 11.6-to-14-GHz subsampling phase-locked loop (PLL) subsampling PLL (SSPLL) using an event-driven frequency-locked loop (ED-FLL) and a harmonic-lock detector (HLD). The ED-FLL becomes active only when a frequency disturbance, $f_{\mathrm {D}}$ , is detected, rapidly corrects the frequency error using a lock-expedition algorithm, …