sampling phase-locked loop (SPLL)

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A Bio-Impedance Readout IC With Phase-Locked Sampling for Real-Time Electrical Impedance Spectroscopy

A Bio-Impedance Readout IC With Phase-Locked Sampling for Real-Time Electrical Impedance Spectroscopy 150 150
Author(s): Seonghyun Park, Song-I Cheon, Haidam Choi, Sein Oh, Sohmyung Ha, Minkyu Je

Abstract:

This article presents an electrical bio-impedance (bioZ) spectroscopy integrated circuit (IC) that achieves both high-throughput and high-accuracy. The proposed phase-locked sampling (PLS) scheme, which employs a sampling phase-locked loop (SPLL) and a reference resistor ( $R_{\textit {REF}}$ ), enables fast and precise impedance demodulation. By extracting the impedance components through sampling …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3704052
Publisher: IEEE

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A Low-Jitter Fractional-N Sampling PLL With Voltage-Domain Quantization-Error Cancellation Using a Nonlinearity-Replication Technique

A Low-Jitter Fractional-N Sampling PLL With Voltage-Domain Quantization-Error Cancellation Using a Nonlinearity-Replication Technique 150 150
Author(s): Yuhwan Shin, Juyeop Kim, Junseok Lee, Yongwoo Jo, Jaehyouk Choi

Abstract:

This work presents a low-jitter, low-fractional-spur fractional- $N$ digital sampling phase-locked loop (SPLL) that generates output frequencies from 10.4to 11.8GHz. Conventional fractional- $N$ PLLs employ a digital-to-time converter (DTC) to cancel the quantization error (Q-error) of the delta-sigma modulator ( $Delta Sigma $ M). To address the nonlinearity (NL) of the DTC, …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3681940
Publisher: IEEE

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