Regulation

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A Fast Transient Response Fully Integrated LDO With a Novel Resetting Oscillator Control Method

A Fast Transient Response Fully Integrated LDO With a Novel Resetting Oscillator Control Method 150 150
Author(s): Masoud Kargaran, Amir Besharati Rad, Ali Medi

Abstract:

This article introduces a novel resetting oscillator regulator (ROR) control method for low-dropout (LDO) regulators, designed to achieve fast settling times for both load and reference input steps. The proposed ROR integrates a high-speed loop that independently functions as an oscillator in a closed-loop configuration, along with a separate high-rate …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3607941
Publisher: IEEE

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A Unified Early-Warning AVFS Design With Path Activation-Aware Monitoring Point Optimization

A Unified Early-Warning AVFS Design With Path Activation-Aware Monitoring Point Optimization 150 150
Author(s): Cai Li, Kaize Zhou, Junyi Qian, Haochang Zhi, Weiwei Shan

Abstract:

This work proposes a unified early-warning adaptive voltage-frequency scaling (AVFS) system that offers a practical low-power solution for commercial IoT devices. First, a path activation-aware monitoring point optimization strategy is proposed to mitigate the risk of illegal voltage scaling. The strategy combines the path activation evaluation with the required timing …

Published in: IEEE Solid-State Circuits Letters
Page(s): 229 – 232
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3593960
Publisher: IEEE

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Digital Low-Dropout Regulator-Assisted Buck DC-DC Converter Achieving 68-mV Droop Voltage and 95.5% Efficiency

Digital Low-Dropout Regulator-Assisted Buck DC-DC Converter Achieving 68-mV Droop Voltage and 95.5% Efficiency 150 150
Author(s): Yichen Xu, Zhaoqing Wang, Rentao Wan, Suhwan Kim, Minxiang Gong, Ram Krishnamurthy, Xin Zhang, Mingoo Seok

Abstract:

This paper proposes a digital low-dropout regulator (DLDO)-assisted buck converter featuring one-step computational droop compensation and DLDO feedback-controlled current handover. The 28-nm test chip achieves a 68-mV droop voltage and a 112-ns settling time for a 1A/0.8ns load step while maintaining a high peak efficiency of 95.5%.

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3581844
Publisher: IEEE

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