Optical signal processing

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An Antenna-to-Bits F-Band 120-Gbps CMOS RF-64QAM Receiver

An Antenna-to-Bits F-Band 120-Gbps CMOS RF-64QAM Receiver 150 150
Author(s): Youssef O. Hassan, Mohammad Oveisi, Zisong Wang, Payam Heydari

Abstract:

A CMOS 100–140-GHz end-to-end receiver (RX) is presented that integrates the antenna input all the way to the bitstream output, while demodulating 64QAM/16QAM/QPSK entirely in the analog domain. A sequential asynchronous demodulation method enables 120-Gbps operation at a notably small baseband power consumption. Fabricated in a 22-nm FDSOI …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3648748
Publisher: IEEE

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A Machine Learning-Inspired PAM-4 Transceiver for Medium-Reach Wireline Links

A Machine Learning-Inspired PAM-4 Transceiver for Medium-Reach Wireline Links 150 150
Author(s): Ramin Javadi, Tejasvi Anand

Abstract:

This article presents an energy-efficient machine learning-inspired PAM-4 wireline transceiver that leverages data encoding at the transmitter (Tx) and feature extraction with classification at the receiver (Rx) to compensate for channel loss ranging from 13 to 26 dB, while maintaining the bit error rate (BER)<10-11. A new consecutive symbol-to-center (CSC) encoding …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3616072
Publisher: IEEE

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A 32 Gb/s 0.36 pJ/bit 3 nm Chiplet IO Using 2.5-D CoWoS Package With Real-Time and Per-Lane CDR and Bathtub Monitoring

A 32 Gb/s 0.36 pJ/bit 3 nm Chiplet IO Using 2.5-D CoWoS Package With Real-Time and Per-Lane CDR and Bathtub Monitoring 150 150
Author(s): Junhui Gu, John Ma, Azhar Ahmed Chowdhury, Jianmin Guo, Xin Zhang, Jackson Ding, Hui Wang, Ken Chang

Abstract:

This article presents a high-density, single-ended non return to zero (NRZ) chiplet I/O implemented with 3 nm CMOS technology on a 2.5-D chip-on-wafer-on-substrate (CoWoS) interposer, accommodating trace lengths up to 2 mm. The design features 216 data lanes, each operating at 32 Gb/s. For the tested 2-mm trace, the channel insertion loss …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1289 – 1298
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3545483
Publisher: IEEE

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