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A Modular Ring-Oscillator Array Chip for Accurate Stress Testing of CMOS Aging Mechanisms

A Modular Ring-Oscillator Array Chip for Accurate Stress Testing of CMOS Aging Mechanisms 150 150

Abstract:

Ring-oscillator (RO) circuits have historically been used to characterize the performance of CMOS technologies, as they can easily expose both process variability and aging through a straightforward circuit structure. ROs are widely employed to study degradation mechanisms such as bias temperature instability (BTI) and hot carrier degradation (HCD), which progressively …

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A 70-GHz Bandwidth Amplifier With Integrated Differential Bridged T-coil Peaking and Uniform Group Delay

A 70-GHz Bandwidth Amplifier With Integrated Differential Bridged T-coil Peaking and Uniform Group Delay 150 150

Abstract:

A two-stage amplifier in 22-nm FD-SOI CMOS integrates a fully-differential bridged T-coil for the first time. Circuit performance is benchmarked against an identical amplifier topology designed with single-ended T-coils (pseudo-differential) and an unpeaked reference. It realizes 70-GHz bandwidth with $12~\pm ~2$ -ps group delay and >10-dB return loss across 90 GHz. Bandwidth …

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Inverse Design of Multilayered Pixelated mm-Wave Power Amplifiers

Inverse Design of Multilayered Pixelated mm-Wave Power Amplifiers 150 150

Abstract:

A topology optimization methodology is presented for the design of multistage, multipath, linear and nonlinear millimeter-wave (mm-Wave) power amplifiers (PAs). Optimization algorithms autonomously generate complete multilayered PA core layouts, including actives and passives, with minimal human intervention in just a few days. Experimental results from fabricated linear and nonlinear W-band …

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Comprehensive Device to System Co-Design for SOT-MRAM at the 7 nm Node

Comprehensive Device to System Co-Design for SOT-MRAM at the 7 nm Node 150 150

Abstract:

This work presents a comprehensive spin-orbit torque (SOT)-based magnetic random access memory (MRAM) design at the 7 nm technology node, spanning from device-level characteristics to system-level power performance area (PPA). At the device level, we show the tradeoffs among the write current, error rate, and time, based on mircomagnetic simulations. …

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A 240-GHz Sub-THz Direct-Conversion Transmitter With I/Q Phase Calibration in 40-nm CMOS

A 240-GHz Sub-THz Direct-Conversion Transmitter With I/Q Phase Calibration in 40-nm CMOS 150 150

Abstract:

A 240-GHz direct-conversion transmitter (TX), consisting of an LO chain and fundamental I/Q mixers, is proposed for sub-THz communication applications. The LO chain integrates phase-shifter-embedded impedance matching networks (IMNs) and frequency tripler with an optimized harmonic IMN, delivering I/Q LO signals at 240 GHz with high output power, 360° phase …

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A 302.5-GHz 30.9-dB-Gain THz Amplifier in 65-nm CMOS

A 302.5-GHz 30.9-dB-Gain THz Amplifier in 65-nm CMOS 150 150

Abstract:

A 302.5-GHz high-gain CMOS THz amplifier is proposed in this work. An electromagnetic (EM) modeling approach, verified by transistor measurements, is employed to optimize transistor layout, effectively reducing gate resistance and drain-to-gate capacitance. This significantly enhances the transistor’s maximum oscillation frequency $f_{mathrm {max }}$ from 239.7 to 367.5 GHz. Furthermore, a $…

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