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A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM With Metal Wire-R Tracking and Sequential Access-Aware Dynamic Power Reduction

A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM With Metal Wire-R Tracking and Sequential Access-Aware Dynamic Power Reduction 150 150
Author(s): Tomotaka Tanaka, Koji Nii, Yuichiro Ishii, Makoto Yabuuchi, Yumito Aoyagi, Masaya Hamada, Kazuto Mizutani, Hidehiro Fujiwara, Isabel Wang, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang

Abstract:

This article presents a 2-read/write (2RW) pseudo dual-port (PDP) static random access memory (SRAM) macro implemented in advanced 3nm Fin-FET technology, achieving a competitive bit density of 19.87Mbit/mm2 for advanced nodes. To address challenges in process scaling, reliability under process voltage temperature variations, and dynamic power consumption, two …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3682256
Publisher: IEEE

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A 12-bit 1-GS/s Current-Steering DAC With Paired Current Source Switching Background Mismatch Calibration

A 12-bit 1-GS/s Current-Steering DAC With Paired Current Source Switching Background Mismatch Calibration 150 150
Author(s): Chang-Un Park, Jae-Hyun Chung, Chunsuk Kim, Hyun-Woo Shin, Charlie Tahar, Seung-Tak Ryu

Abstract:

This article presents a spur-suppressed background calibration technique for high-speed current-steering digital-to-analog converters (DACs), based on a paired current source (CS) switching scheme. In conventional background calibration, periodic switching of CSs to and from the calibration mode introduces unwanted glitches that appear as spurious tones. The proposed technique introduces an …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3668788
Publisher: IEEE

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A 65-nm CMOS Machine-Learning-Enhanced Bandwidth-Efficient LiDAR

A 65-nm CMOS Machine-Learning-Enhanced Bandwidth-Efficient LiDAR 150 150
Author(s): Pooya Poolad, Foad Arvani, Bahaa Radi, Ping-Hsuan Hsieh, Tony Chan Carusone

Abstract:

We present a proof-of-concept light detection and ranging (LiDAR) signal processing architecture that integrates a machine-learning-enhanced processing unit (PU) with on-chip time-to-digital converters (TDCs) to reduce bandwidth and memory requirements in SPAD-based direct time-of-flight (dToF) systems. The proposed architecture fits a Gaussian mixture model (GMM) to photon arrival time distributions …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3652972
Publisher: IEEE

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An 11.95-ENOB 560-MS/s Amplifier-Switching Subranging Analog-to-Digital Converter With Multi-Threshold Comparators

An 11.95-ENOB 560-MS/s Amplifier-Switching Subranging Analog-to-Digital Converter With Multi-Threshold Comparators 150 150
Author(s): Ritaro Takenaka, Tetsuya Iizuka

Abstract:

This article proposes a 14-bit, 560-MS/s subranging analog-to-digital converter (ADC) that employs an amplifier-switching architecture with multi-threshold comparators. The proposed amplifier-switching architecture reuses a flash quantizer multiple times during subranging conversion by amplifying the residue voltage with an appropriate gain at each quantization step. This approach reduces the required …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3647024
Publisher: IEEE

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A High-Speed D-FF and a 11-Bit Up-Down Counter Using Unipolar Oxide TFTs on a Flexible Foil

A High-Speed D-FF and a 11-Bit Up-Down Counter Using Unipolar Oxide TFTs on a Flexible Foil 150 150
Author(s): Suyash Shrivastava, Pydi Ganga Bahubalindruni

Abstract:

This manuscript presents an experimental characterization of a novel high speed D flip-flop (D-FF). The circuit was fabricated on a $27\mu $ m thick flexible polyimide substrate using a nMOS only, single gate amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transistor (TFT) technology. Reliable response of the D-FF was noticed from measurements up to …

Published in: IEEE Solid-State Circuits Letters
Page(s): 373 – 376
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3636192
Publisher: IEEE

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A Benchmark of Cryo-CMOS Dynamic Comparators in a 40 nm Bulk CMOS Technology

A Benchmark of Cryo-CMOS Dynamic Comparators in a 40 nm Bulk CMOS Technology 150 150
Author(s): Bram Veraverbeke, Filip Tavernier

Abstract:

All cryo-CMOS quantum-classical control interfaces require an analog-to-digital converter (ADC) bridging the analog qubits and the digital control logic. Dynamic comparators play a crucial role in the precision, speed, and power consumption of these ADCs. Yet, their performance is severely impacted by the cryogenic environment. Therefore, this letter benchmarks, for …

Published in: IEEE Solid-State Circuits Letters
Page(s): 317 – 320
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3618161
Publisher: IEEE

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Ultra-Low-Power Dynamic-Bias Comparators With Self-Clocked Latch in 65-nm CMOS

Ultra-Low-Power Dynamic-Bias Comparators With Self-Clocked Latch in 65-nm CMOS 150 150
Author(s): Anojh Kumaran Rajendra, Harijot Singh Bindra, Bram Nauta

Abstract:

This article introduces two comparators featuring a dynamic-bias preamplifier and self-clocked latches, tailored for ultra-low-power and medium-speed applications with <500- $\mu $ V input-referred noise (IRN). The proposed self-clocked latches are activated by the preamplifier outputs and therefore operate with a lower common-mode current, which in turn minimizes the crowbar current …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3612157
Publisher: IEEE

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A 38.1 fJ/Bit Capacitive-Latch True Random Number Generator Featuring Both Autozeroed Inverter Mismatch and Accelerated Evaluation

A 38.1 fJ/Bit Capacitive-Latch True Random Number Generator Featuring Both Autozeroed Inverter Mismatch and Accelerated Evaluation 150 150
Author(s): Woojin Lee, Changmin Sim, Changjoo Kim, Jinwoo Jeon, Hyundo Jung, Taihyun Kim, Chulwoo Kim

Abstract:

This work presents a capacitive-latch (C-latch) true random number generator (TRNG) that achieves both inverter mismatch autozeroing and accelerated evaluation by utilizing coupling capacitors. The proposed C-latch TRNG samples the mismatch between inverter equalization voltages through coupling capacitors during the equalization phase, effectively autozeroing inverter mismatch and enabling high-entropy raw …

Published in: IEEE Solid-State Circuits Letters
Page(s): 265 – 268
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3608187
Publisher: IEEE

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