Large scale integration

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A CMOS Probabilistic Computing Chip with Hardware-Aware Learning

A CMOS Probabilistic Computing Chip with Hardware-Aware Learning 150 150
Author(s): Jinesh Jhonsa, William Whitehead, Yihao Wu, David McCarthy, Shuvro Chowdhury, Kerem Y. Camsari, Luke Theogarajan

Abstract:

This work demonstrates a compact probabilistic computing system based on a physics-inspired p-bit architecture with 440 interacting spins configured in a Chimera graph and occupying 0.44 mm² of silicon area. Area efficiency is achieved through a current-mode neuron update circuit and a mixed-signal design approach that integrates pitch-matched standard-cell analog blocks with …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3689506
Publisher: IEEE

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A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM With Metal Wire-R Tracking and Sequential Access-Aware Dynamic Power Reduction

A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM With Metal Wire-R Tracking and Sequential Access-Aware Dynamic Power Reduction 150 150
Author(s): Tomotaka Tanaka, Koji Nii, Yuichiro Ishii, Makoto Yabuuchi, Yumito Aoyagi, Masaya Hamada, Kazuto Mizutani, Hidehiro Fujiwara, Isabel Wang, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang

Abstract:

This article presents a 2-read/write (2RW) pseudo dual-port (PDP) static random access memory (SRAM) macro implemented in advanced 3nm Fin-FET technology, achieving a competitive bit density of 19.87Mbit/mm2 for advanced nodes. To address challenges in process scaling, reliability under process voltage temperature variations, and dynamic power consumption, two …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3682256
Publisher: IEEE

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