Harmonic analysis

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A Ring-Oscillator-Based Digital Harmonic-Mixing Fractional-N PLL

A Ring-Oscillator-Based Digital Harmonic-Mixing Fractional-N PLL 150 150
Author(s): Hongyu Lu, Nader Fathy, Patrick P. Mercier

Abstract:

This letter presents a low-jitter digital harmonic-mixing fractional- $N$ phase-locked loop (PLL) using a ring oscillator. To extend the loop bandwidth, a mixer with unity gain in the phase domain is adopted, which helps suppress phase noise of the phase detector and delta-sigma modulator. Furthermore, to reduce mixing harmonics that …

Published in: IEEE Solid-State Circuits Letters
Page(s): 57 – 60
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3654239
Publisher: IEEE

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A 298–334-GHz Scalable Injection-Locked Phased-Array Radiator With Second-Subharmonic-Termination-Assisted Waveform Formulation for Power Enhancement

A 298–334-GHz Scalable Injection-Locked Phased-Array Radiator With Second-Subharmonic-Termination-Assisted Waveform Formulation for Power Enhancement 150 150
Author(s): Meng Yang, Liang Wu

Abstract:

This article introduces an injection-locked $4\times 2$ phased-array radiator featuring scalability in both horizontal and vertical dimensions. The system architecture is constructed by sequentially cascading four identical phase-shifting and frequency-quadrupling (PSFQ) elements in a chain-like configuration and then cohering two such chains, thereby achieving global frequency synchronization. Particularly, phase shifting and …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3624563
Publisher: IEEE

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A Compact Current-Reusing 6-mW 66–92 GHz Frequency Quadrupler With 5% Peak Power Added Efficiency and >36 dBc Harmonic Rejection in 22-nm FDSOI CMOS

A Compact Current-Reusing 6-mW 66–92 GHz Frequency Quadrupler With 5% Peak Power Added Efficiency and >36 dBc Harmonic Rejection in 22-nm FDSOI CMOS 150 150
Author(s): Shankkar Balasubramanian, Kristof Vaesen, Piet Wambacq, Carsten Wulff

Abstract:

This letter presents a frequency quadrupler with 32% fractional bandwidth (66–92 GHz) and 5% peak power-added efficiency (PAE), capable of operating with an input power of 0 dBm. The quadrupler consisting of two cascaded frequency doublers uses a multiport driven push-push complementary architecture for the first stage to generate differential signals for the second …

Published in: IEEE Solid-State Circuits Letters
Page(s): 301 – 304
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3614381
Publisher: IEEE

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A 240-GHz Sub-THz Direct-Conversion Transmitter With I/Q Phase Calibration in 40-nm CMOS

A 240-GHz Sub-THz Direct-Conversion Transmitter With I/Q Phase Calibration in 40-nm CMOS 150 150
Author(s): Chun-Sheng Lin, Chih-Hsueh Lin, Chun-Hsing Li

Abstract:

A 240-GHz direct-conversion transmitter (TX), consisting of an LO chain and fundamental I/Q mixers, is proposed for sub-THz communication applications. The LO chain integrates phase-shifter-embedded impedance matching networks (IMNs) and frequency tripler with an optimized harmonic IMN, delivering I/Q LO signals at 240 GHz with high output power, 360° phase …

Published in: IEEE Solid-State Circuits Letters
Page(s): 225 – 228
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3592246
Publisher: IEEE

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A Millimeter-Wave Standing-Wave Oscillator With Frequency-Specific Wave-Velocity Control Demonstrating Class-F Effects

A Millimeter-Wave Standing-Wave Oscillator With Frequency-Specific Wave-Velocity Control Demonstrating Class-F Effects 150 150
Author(s): Wei-Yu Lin, Jun-Chau Chien

Abstract:

Implementing dual-resonance class-F oscillators with transformer feedback beyond 60 GHz poses significant challenges due to the limited third-harmonic tank impedance when using small coils with low coupling factors. To address these limitations and leverage the phase noise advantages of class-F operation, this letter introduces a standing-wave oscillator (SWO) topology featuring an …

Published in: IEEE Solid-State Circuits Letters
Page(s): 181 – 184
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3578942
Publisher: IEEE

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A 9-GHz Low-In-Band Noise Sub-Sampling-Chopper PLL With Charge-Share Canceling Technique

A 9-GHz Low-In-Band Noise Sub-Sampling-Chopper PLL With Charge-Share Canceling Technique 150 150
Author(s): Xiangjian Kong, Kai Xu, Huanlin Xie, Mingchao Jian, Hao Lian, Robert Bogdan Staszewski, Chunbing Guo

Abstract:

This article presents a low-jitter sub-sampling chopper phase-locked loop (SS-CPLL) that incorporates a novel chopping charge pump (C-CP) to mitigate 1/f noise in short-channel devices operating at a low supply voltage of 0.75 V. A charge-share cancellation technique is introduced to suppress ripple generated by residual charge from the previous reference …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1384 – 1396
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3532504
Publisher: IEEE

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