hardware security

  • No Comments

Verifica: Near-Memory Symbolic Interval Computing Formal Neural Network Verification Accelerator

Verifica: Near-Memory Symbolic Interval Computing Formal Neural Network Verification Accelerator 150 150
Author(s): Edward Jongyoon Choi, Byeongseon Choi, Jiho Chun, Minkyu Je, Bongjin Kim

Abstract:

Formal robustness verification of neural networks is essential for deploying machine learning (ML) systems in safety-critical applications. However, existing verification frameworks are predominantly software-based, incurring prohibitive computational costs and long runtimes, severely limiting scalability and practical deployment. Although symbolic interval analysis enables scalable over-approximate verification, its effectiveness is limited by …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3707324
Publisher: IEEE

View on IEEE Xplore

  • No Comments

GUARD: A Clock and Voltage Glitch Detector With On-Demand Protection

GUARD: A Clock and Voltage Glitch Detector With On-Demand Protection 150 150
Author(s): Mao Li, Sanu K. Mathew, Vivek De, Mingoo Seok

Abstract:

This article presents GUARD, a fully digital, variation-tolerant detector for clock and voltage glitch attacks, featuring an integrated on-demand protection mechanism. Fabricated in 28-nm CMOS, GUARD provides robust security for digital systems by monitoring the system clock for maliciously injected faults. It employs a pair of optimized time-to-digital converters (TDCs) …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3696209
Publisher: IEEE

View on IEEE Xplore

  • No Comments

Design and Analysis of a Three-Stream STT-MTJ TRNG With XOR and Majority Voter Logic as Postprocessing Architectures

Design and Analysis of a Three-Stream STT-MTJ TRNG With XOR and Majority Voter Logic as Postprocessing Architectures 150 150
Author(s): M. Satwik Rai, Akshaja Kanugovi, Vinod Kumar Joshi

Abstract:

True random number generators (TRNGs) are critical for hardware security, providing unpredictable entropy for cryptographic applications. Spin-transfer torque magnetic tunnel junction (STT-MTJ) devices offer a promising entropy source due to their low-power consumption, nonvolatility, and stochastic switching behavior. This work presents an MTJ-based TRNG that produces three independent bit streams. …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 36 – 44
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3671608
Publisher: IEEE

View on IEEE Xplore

  • No Comments

An Eye-Opening Arbiter PUF With Auto-Error Detection and PVT-Robust Masking Achieving a BER of 2e-8

An Eye-Opening Arbiter PUF With Auto-Error Detection and PVT-Robust Masking Achieving a BER of 2e-8 150 150
Author(s): Bjoern Driemeyer, Holger Mandry, David-Peter Wiens, John G. Kauffman, Joachim Becker, Maurits Ortmanns

Abstract:

A hybrid ring oscillator (RO)/ arbiter physical unclonable function (PUF) is implemented in a 28-nm CMOS, where two competing ROs accumulate a sufficiently large phase difference exceeding a predefined deadzone (DZ). The resulting eye-opening arbiter (EOA) architecture enables a prediction of PUF bit stability over temperature change (from −40 °C to $125~^{\…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3663673
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 168 nW to 44.3 Mb/s Adaptable TRNG With 400 mV Attack-Resilient Hybrid RO Core

A 168 nW to 44.3 Mb/s Adaptable TRNG With 400 mV Attack-Resilient Hybrid RO Core 150 150
Author(s): Berkay Özbek, Timothy G. Constandinou

Abstract:

This letter presents an adaptable ring oscillator (RO)-true random number generator (TRNG) that removes the fixed power–throughput tradeoff by selecting delay-cell physics at run time. A hybrid core uses a current-starved inverter in low-power (LP) mode to amplify slew-limited jitter for high bit-efficiency at low frequency, and a …

Published in: IEEE Solid-State Circuits Letters
Page(s): 325 – 328
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3621413
Publisher: IEEE

View on IEEE Xplore

  • No Comments

High-Entropy Analog-Based Strong Physical Unclonable Function With Area-to-Entropy-ratio of 166 F2/bit

High-Entropy Analog-Based Strong Physical Unclonable Function With Area-to-Entropy-ratio of 166 F2/bit 150 150
Author(s): Alessandro Catania, Sebastiano Strangio, Maksym Paliy, Christian Sbrana, Michele Bertozzi, Giuseppe Iannaccone

Abstract:

In this letter, we present a high-entropy strong physically unclonable function (PUF) utilizing weak-inversion current mirrors implemented in a standard 65-nm CMOS technology. Each response bit of the proposed PUF relies on the threshold voltage differences of minimum-sized transistors arranged in a $32\times 32$ matrix. The analog operating principle enables encoding …

Published in: IEEE Solid-State Circuits Letters
Page(s): 309 – 312
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3616263
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 38.1 fJ/Bit Capacitive-Latch True Random Number Generator Featuring Both Autozeroed Inverter Mismatch and Accelerated Evaluation

A 38.1 fJ/Bit Capacitive-Latch True Random Number Generator Featuring Both Autozeroed Inverter Mismatch and Accelerated Evaluation 150 150
Author(s): Woojin Lee, Changmin Sim, Changjoo Kim, Jinwoo Jeon, Hyundo Jung, Taihyun Kim, Chulwoo Kim

Abstract:

This work presents a capacitive-latch (C-latch) true random number generator (TRNG) that achieves both inverter mismatch autozeroing and accelerated evaluation by utilizing coupling capacitors. The proposed C-latch TRNG samples the mismatch between inverter equalization voltages through coupling capacitors during the equalization phase, effectively autozeroing inverter mismatch and enabling high-entropy raw …

Published in: IEEE Solid-State Circuits Letters
Page(s): 265 – 268
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3608187
Publisher: IEEE

View on IEEE Xplore

Search this website