feed-forward equalizer (FFE)

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A 42-Gb/s PAM-3 Transmitter With a CML Driver and a Dual-Mode Encoder for Process-Variation-Tolerant Middle-Level Generation

A 42-Gb/s PAM-3 Transmitter With a CML Driver and a Dual-Mode Encoder for Process-Variation-Tolerant Middle-Level Generation 150 150
Author(s): Seungwoo Park, Taehwan Kim, Changmin Sim, Seongcheol Kim, Junseob So, Hwaseok Shin, Seon-Been Lee, Chulwoo Kim

Abstract:

This letter presents a 42-Gb/s differential PAM-3 transmitter using a current-mode logic (CML) driver and a dual-mode 3B2T encoder for process-variation-tolerant middle-level (M-level) generation. The encoder selects between two M-level encoding schemes to compensate for load-resistor and driver-current-path mismatches with minimal logic overhead, reducing the standard deviation of …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3720204
Publisher: IEEE

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A 108-Gb/s PAM-8 CTLE + FFE Receiver Front-End With 1.4-Vppd Input Range in 28-nm CMOS

A 108-Gb/s PAM-8 CTLE + FFE Receiver Front-End With 1.4-Vppd Input Range in 28-nm CMOS 150 150
Author(s): Sangwan Lee, Heedo Jeong, Hanhee Jo, Hwanseok Jung, Jaeduk Han

Abstract:

This article presents a 108-Gb/s 8-level pulse amplitude modulation (PAM-8) receiver front-end capable of handling a wide input dynamic range to overcome the signal-to-noise ratio (SNR) versus linearity tradeoff in higher-order modulation schemes. The proposed architecture employs a multi-path continuous-time linear equalizer (CTLE) with a bias-shifting technique, which splits …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3713392
Publisher: IEEE

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