A 1.6-GS/s 13.9-mW 80.2-dB SFDR Single-Channel Pipelined ADC With Dual-Phase Hybrid Amplification https://sscs.ieee.org/wp-content/themes/movedo/images/empty/thumbnail.jpg 150 150 https://secure.gravatar.com/avatar/8fcdccb598784519a6037b6f80b02dee03caa773fc8d223c13bfce179d70f915?s=96&d=mm&r=g
Abstract:
In this article, we present a 1.6-GS/s single-channel pipelined analog-to-digital converter (ADC). In high-speed ADC designs, residue amplifiers (RAs) face stringent constraints on their amplification time and accuracy. To relax these requirements, first, we propose a dual-phase amplification stage to isolate the serial operations between the second-stage sampling and …