digital-to-analog converter (DAC)

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A 1.59 pJ/b 112-Gb/s PAM-4 and 1.06 pJ/b 168-Gb/s PAM-8 Resistor-Less 7-Bit SST DAC-Based Transmitter with 8-Tap FFE

A 1.59 pJ/b 112-Gb/s PAM-4 and 1.06 pJ/b 168-Gb/s PAM-8 Resistor-Less 7-Bit SST DAC-Based Transmitter with 8-Tap FFE 150 150
Author(s): Yao-Hung Tsai, Ming-Han Chuang, Shen-Iuan Liu

Abstract:

A resistor-less 7-bit source-series-termination (SST) DAC-based transmitter (TX) with an 8-tap feedforward equalizer (FFE) is presented. Three different resistor-less SST segments (SSTSs) are employed to achieve low capacitance, compact area, and scaling friendliness. To reduce the output jitter of 4:1 multiplexer due to the inter-symbol-interference (ISI), the dual-feedback equalizer (DFEQ) is …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3722281
Publisher: IEEE

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A 32-Channel 85.4 dB SNDR Time-Multiplexed Neural Recording Front-End Achieving Within-Conversion Artifact Recovery

A 32-Channel 85.4 dB SNDR Time-Multiplexed Neural Recording Front-End Achieving Within-Conversion Artifact Recovery 150 150
Author(s): Arindam Mandal, Chi-Hsiang Huang, Julian Arenas, Wei-En Lee, Kevin D. Patino-Sosa, Philip Anschutz, Amanda Jacob, Keshav Ramachandra, Samuel Sober, Muhannad S. Bakir, Shaolan Li, Visvesh S. Sathe

Abstract:

This article presents a 32-channel time-multiplexed highly digital neural recording front-end (RFE) that exhibits sub- $8.8~\mu $ s recovery latency from large stimulation artifacts while delivering high-resolution data at the Nyquist rate. The RFE is time-shared across 32 channels for low-frequency electrocorticography (ECoG) recording and across four channels for high-frequency action potentials (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1053 – 1067
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3643367
Publisher: IEEE

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A 12-bit 1-GS/s Current-Steering DAC With Paired Current Source Switching Background Mismatch Calibration

A 12-bit 1-GS/s Current-Steering DAC With Paired Current Source Switching Background Mismatch Calibration 150 150
Author(s): Chang-Un Park, Jae-Hyun Chung, Chunsuk Kim, Hyun-Woo Shin, Charlie Tahar, Seung-Tak Ryu

Abstract:

This article presents a spur-suppressed background calibration technique for high-speed current-steering digital-to-analog converters (DACs), based on a paired current source (CS) switching scheme. In conventional background calibration, periodic switching of CSs to and from the calibration mode introduces unwanted glitches that appear as spurious tones. The proposed technique introduces an …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3668788
Publisher: IEEE

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