Solid-State Circuits Society (SSCS) Open Journal Webinar Series
Solid-State Circuits Society (SSCS) Open Journal Webinar Series
Please join us for the inaugural Solid-State Circuits Society (SSCS) Open Journal Webinar Series. This series will feature two talks on two papers from SSCS open journals: IEEE Open Journal of the Solid-State Circuits Society (OJ-SSCS) and IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JxCDC).
Design Techniques for High-Speed Wireline Transmitters
Presented by Behzad Razavi
Wednesday, December 7, 2022 at 11:00 AM ET
Published in: IEEE Open Journal of the Solid-State Circuits Society (Volume: 1)
Abstract: Wireline transmitters operating at tens of gigabits per second pose challenging design issues ranging from limited bandwidths to severe sensitivity to jitter. This paper presents a number of analog and digital circuit techniques that allow data rates as high as 80 Gb/s in 45-nm CMOS technology. A PAM4 prototype delivers an output swing of 630 mV pp with a clock jitter of 205 fs rms while drawing 44 mW.
Author: Behzad Razavi
Bio: Beh
zad Razavi is Professor of Electrical Engineering at UCLA, where he conducts research on analog and RF integrated circuits. Prof. Razavi has served as an IEEE Distinguished Lecturer and published more than 200 papers and eight books. He has received nine IEEE best paper awards and six teaching and education awards, and his books have been published in seven languages. He received the IEEE Pederson Award in Solid-State Circuits and was recognized as one of the top ten authors in the 50-year history of the IEEE International Solid-State Circuits Conference. He is a member of the US National Academy of Engineering and a fellow of the US National Academy of Inventors.
IGZO CIM: Enabling in-memory computations using multi-level capacitorless Indium Gallium Zinc Oxide based embedded DRAM technology
Presented by Jaydeep P. Kulkarni and Siddhartha Raman
Tuesday, December 13, 2022 at 10:00 AM ET
Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits ( Volume: 8, Issue: 1, June 2022)
Abstract: Compute-in-memory (CIM) is a promising approach for efficiently performing data-centric computing (such as neural network computations). Among the multiple semiconductor memory technologies, embedded DRAM (eDRAM), which integrates the DRAM bit cell with high-performance logic transistors, can enable efficient CIM designs. However, the silicon-based eDRAM technology suffers from poor retention time-incurring significant refresh power overhead. However, eDRAM using back-end-of-line (BEOL) integrated C -axis aligned crystalline (CAAC) indium–gallium–zinc–oxide (IGZO) transistors, exhibiting extreme low leakage, is a promising memory technology with lower refresh power overhead. A long retention time in IGZO eDRAM can enable multilevel cell functionality, which can improve its efficacy in CIM applications. In this article, we explore a capacitorless IGZO eDRAM-based multilevel cell, capable of storing 1.5 bits/cell for CIM designs focused on deep neural network (DNN) inference applications. We perform a detailed design space exploration of IGZO eDRAM sensitivity to process temperature variations for read, write, and retention operations followed by architecture-level simulations comparing performance and energy for different workloads. The effectiveness of IGZO eDRAM-based CIM architecture is evaluated using a representative neural network, and the proposed approach achieves 82% Top-1 inference accuracy for the CIFAR-10 dataset, compared with 87% software accuracy with high bit cell storage density.
Authors: Siddhartha Raman Sundara Raman; Shanshan Xie; Jaydeep P. Kulkarni.
Bio: Jaydeep Kulkarni received a B.E. degree from the University of Pune, India, in 2002, an M. Tech degree from the Indian Institute of Science (IISc) in 2004, and a Ph.D. degree from Purdue University in 2009. During 2009-2017, he worked as a Research Scientist at Intel Circuit Research Lab in Hillsboro, OR. Currently, he is an assistant professor in the department of electrical and computer engineering at the University of Texas at Austin, a fellow of Silicon Labs Chair in electrical engineering, and a fellow of AMD chair in computer engineering. He has filed 36 patents, published two book chapters, and 100+ papers in refereed journals and conferences. His research is focused on machine learning hardware accelerators, in-memory computing, DTCO for emerging nano-devices, heterogeneous and 3D integrated circuits, hardware security, and cryogenic computing.
He received the 2004 best M. Tech student award from IISc Bangalore, the 2008 Intel Foundation Ph.D. fellowship award, the 2010 Purdue school of ECE outstanding doctoral dissertation award, the 2015 IEEE Transactions on VLSI systems best paper award, the 2015 SRC outstanding industrial liaison award, 2018, 2019 Micron Foundation Faculty Awards, and 2020 Intel Rising Star Faculty Award, SF CAREER Award, and SRC Innovation Award. He has participated in technical program committees of the VLSI Symposium, CICC, ASSCC, DAC, ICCAD, ISLPED, and AICAS conferences. During his tenure at Intel Labs, he served as a distinguished industrial lecturer for IEEE Circuits and Systems Society and as an industrial liaison for SRC and NSF programs. He has served as a TPC co-chair and general co-chair for 2017 and 2018 ISLPED, respectively. He is currently an associate editor for IEEE Solid-State Circuit Letters, IEEE Transactions on VLSI Systems, IEEE Transactions on Circuits and Systems -II, and a guest editor for IEEE Micro. He is currently a distinguished lecturer for the IEEE Solid State Circuit Society and the IEEE Electron Device Society. He is also the chair of the IEEE solid-state circuits society and circuits and systems society central Texas joint chapter. He is a senior member of IEEE and the National Academy of Inventors.
Bio: Siddhartha Raman Sundara Raman received the B.Eng. degree from the Birla Institute of Technology and Science, Pilani, India and the M.Sc. degree in Electrical and Computer Engineering from The University of Texas at Austin, USA and is currently pursuing a Ph.D in Electrical and Computer Engineering(ECE) from The University of Texas at Austin. He interned at the National University of Singapore and worked on spintronic circuits during his undergraduate study. His current research interests include compute-in-memory, cryogenic computing, and device-circuit-architecture for optimization algorithms