Special Section on High-Performance Fractional-N Phase-Locked Loops
Aim and Scope
Phase-locked loops (PLLs) serve as the cornerstone of modern electronic systems of modern electronic systems. The rapid evolution of 5G/6G wireless transceivers and the expansion of large-scale AI clusters have catalyzed an unprecedented demand for ultra-low-jitter clocking. To support high-order modulation schemes and next-generation high-speed wireline links, system clocks must now deliver root-mean-square (RMS) jitter in the deep sub-picosecond regime. Furthermore, preserving signal-to-noise ratio (SNR) integrity at millimeter-wave frequencies has emerged as a critical bottleneck for both wireless and wireline throughput.
Beyond integrated phase noise, the rigorous suppression of reference and fractional spurs is essential to meet stringent spectral emission masks and ensure the purity required for future communication and AI platforms. This Special Section invites original research and survey papers on advanced frequency synthesis techniques that address the multi-dimensional challenges of achieving ultra-low jitter and high spectral purity alongside wide tuning ranges.
Topics of Interest
Authors are invited to submit papers following the IEEE Open Journal of the Solid-State Circuits Society (OJ-SSCS) guidelines, within the remit of this Special Section call. Topics include (but are not limited to):
- Architectures: Low-jitter analog, digital, and hybrid PLLs; sampling-based, bang-bang, and alternative phase detections.
- Performance Metrics: Advanced spur mitigation and spectral purity enhancement techniques.
- Agile Synthesis: High-linearity FMCW modulation and fast-settling synthesizers for sensing and radar.
- Applications: 200+ Gb/s wireline clocking, phased-array synthesis, automotive radar, and sub-THz generation.
- Digital Assistance: digitally-assisted or ML-enhanced calibration for jitter, spur, and modulation optimization.
- Building Blocks: Ultra-low-noise oscillators, high-resolution TDCs, and DTCs.
Submission Guidelines
All submitted manuscripts are strongly encouraged to
- conform to OJ-SSCS’ normal formatting requirements and page count limits;
- validate principal claims with experimental results;
- be submitted online at: https://mc.manuscriptcentral.com/oj-sscs
Please note that you need to select “High-Performance Phase-Locked Loops” when you submit a paper to this Special Section.
Deadlines
- Special Section Open for Submissions: April 6, 2026
- Paper Submission Deadline: June 10, 2026
- First Notification: July 17, 2026
- Revision Submission: August 10, 2026
- Final Decision: September 14, 2026
- Publication Online: September 25, 2026