Special Section on Energy-Efficient I/O Circuits & Optical Interconnects
Aim and Scope
The explosive growth of AI training and inference workloads, disaggregated computing architectures, and hyperscale data-center networks has pushed electrical I/O and interconnect bandwidth to their physical limits. Chiplet-based heterogeneous integration, co-packaged and near-packaged optics (CPO/NPO), and next-generation optical transceivers are emerging as the leading paths to sustain the bandwidth, energy-efficiency, and reach requirements of modern computing systems. Achieving these gains requires innovative circuit and architecture techniques that jointly optimize energy efficiency (pJ/bit) and bandwidth density (Gb/s/mm, Gb/s/mm²), the two figures of merit that increasingly bound system-level performance in beachfront- and power-limited packages.
This special section focuses on all aspects of energy-efficient, high-bandwidth-density I/O circuits and architectures, emphasizing innovative solutions spanning electrical SerDes, die-to-die chiplet interconnects, silicon photonics, and optical transceivers. Submissions should present advanced technical depth, critical insight, and a forward-looking perspective on where the field is headed, going beyond textbook-style tutorials or simple compilations of prior work. Both original research articles with silicon results and in-depth survey/tutorial papers synthesizing state-of-the-art techniques and future research directions are strongly encouraged.
Topics of Interest
Authors are invited to submit papers following the IEEE Open Journal of the Solid-State Circuits Society (OJ-SSCS) guidelines, within the remit of this Special Section call. Topics include (but are not limited to):
- Energy-efficient, high-bandwidth-density electrical SerDes and die-to-die chiplet interconnect circuits (e.g., 112G/224G+ NRZ/PAM PHYs, UCIe and related standards)
- Silicon photonics devices and optical transceiver circuits, including co-packaged and near-packaged optics (CPO/NPO), drivers, TIAs, and VCSEL-/EML-/modulator-based link architectures
- 2D/2.5D/3D packaging and integration strategies for electrical and optical I/O
- Signal integrity, channel modeling, line coding, and equalization techniques for next-generation interconnects
- Clock generation and distribution, power delivery, thermal management, and reliability considerations for high-density I/O systems
- System- and architecture-level co-design of electrical and optical links for AI/ML scale-in, scale-up, and scale-out fabrics
Submission Guidelines
All submitted manuscripts are strongly encouraged to
- Conform to OJ-SSCS’s normal formatting requirements and page count limits.
- Authors should validate principal claims with experimental results.
- Manuscripts should be submitted online at: https://mc.manuscriptcentral.com/oj-sscs
Please select “Special Section on Energy-Efficient I/O Circuits & Optical Interconnects” when you submit a paper to this Special Section.
Deadlines
- Special Section Open for Submissions: Sept 1, 2026
- Paper Submission Deadline: Nov 6, 2026
- First Notification: December 20, 2026
- Revision Submission: January 10, 2027
- Final Decision: January 30, 2027
- Publication Online: February 14, 2027