Special Issue on Circuits and Systems for Hardware Security
Aim and Scope
Hardware Security has become a significant concern in every aspect of the development of integrated circuits (ICs) that drive the connected information ecosystem. The entire silicon lifecycle, from design, manufacturing, logistics, to even disposal, is affected by the need for traceable, authentic and tamper-free ICs. Novel IC designs of secure applications must also be resilient against hardware Trojans, reverse engineering and physical attacks. Furthermore, the supply chain of secure semiconductors now extends well beyond the silicon die into integrated systems based on chiplets and innovative interconnect and packaging.
This special issue primarily focuses on digital circuits and analog circuits for hardware security. Silicon implementation with measurement results will be highly appreciated. We will also welcome design techniques of security features of Silicon IC chips if the results are reasonably validated by FPGA prototyping or fully explained by simulation at Silicon device level particularly with emerging devices.
Topics of Interest
Authors are invited to submit papers following the IEEE Open Journal of the Solid-State Circuits Society (OJ-SSCS) guidelines, within the remit of this Special Section call. Topics include (but are not limited to):
- Cryptographic engines
- Tamper resilient circuits
- Fault injection attack detection circuits
- Circuits for authenticity of IC chips
- Security Primitives – Physically Unclonable Functions (PUF), True Random Number Generators (TRNG)
- Integration techniques toward trusted semiconductor supply chain
- Secure chiplets, interposers and IC interconnect
- Tamper sensors for passive and active attacks
- Circuit techniques to reduce EM, optical, power and timing leakage
- Circuit techniques to prevent optical, thermal probing
- Circuit techniques to reduce data remanence
- Optimization of storage integrity (Rowhammer, bit-flip, ..)
- Circuit reliability and health monitoring
Submission Guidelines
All submitted manuscripts are strongly encouraged to
- conform to OJ-SSCS’ normal formatting requirements and page count limits;
- validate principal claims with experimental results;
- be submitted online at: https://mc.manuscriptcentral.com/oj-sscs
Please note that you need to select “High-Performance Wireline Transceiver Circuits” when you submit a paper to this Special Issue.
Deadlines
- Special Section Open for Submissions: October 1, 2025
- Paper Submission Deadline: December 15, 2025
- First Notification: January 31, 2026
- Revision Submission: February 28, 2026
- Final Decision: April 15, 2026
- Publication Online: May 5, 2026