Special Section on High Performance Clocking for Next-Generation Computing and Communication Systems

Prof. Wei-Zen Chen, National Yang Ming Chiao Tung University, Hsinchu, Taiwan,
Prof. Masum Hossain, Carleton University, Ottawa, Canada,

With the evolving landscape of wireline and wireless systems, the demand for precise timing reference generation has become increasingly critical. As SerDes I/O data rates exceed 200 Gb/s and advanced wireless transceivers adopt high-order modulation schemes such as 4K-QAM, jitter requirements are becoming more stringent to ensure reliable bit-error-rate (BER) performance.

Moreover, clocking solutions must now be scalable, compact, and energy-efficient to meet the demands of next-generation systems. On the receiver side, timing recovery and lock-point acquisition are pivotal and gaining renewed attention—particularly in the context of advanced modulation technique like multilevel modulation and discrete multitone (DMT) signaling.

In addition to ultra-high-speed links, high-density interconnects such as UCIe require meticulous clock generation and latency matching to support source-synchronous jitter tracking. Concurrently, continued technology scaling has opened the door to alternative clocking architectures that are more digital-friendly and amenable to integration.

This Special Section invites original research and survey papers on advanced clocking techniques that enable communication links for the next-generation communication and AI computing platforms.

Authors are invited to submit papers following the IEEE Open Journal of the Solid-State Circuits Society (OJ-SSCS) guidelines, within the remit of this Special Section call. Topics include (but are not limited to):

• Clock generation for 200+ Gb/s links and beyond 5G wireless transceiver
• Multi-standard low power clock generation and distribution
• Timing recovery for advanced modulation techniques
• High-linearity phase interpolators (PIs)
• Burst-mode clock and data recovery
• PLLs for dynamic frequency scaling
• Digital phase-locked loop
• Calibration techniques for high performance PLLs.

All submitted manuscripts are strongly encouraged to

1. conform to OJ-SSCS’ normal formatting requirements and page count limits;
2. validate principal claims with experimental results;
3. be submitted online at: https://ieee.atyponrex.com/journal/oj-sscs

Please note that you need to select “High Performance Clocking for Next-Generation Computing and Communication Systems” when you submit a paper to this Special Section.

• Special Section Open for Submissions: July 1, 2025
• Paper Submission Deadline: August 31, 2025
• First Notification: October 15, 2025
• Revision Submission: November 10, 2025
• Final Decision: November 30, 2025
• Publication Online: December 15, 2025