Special Issue on High-Performance Wireline Transceiver Circuits

OJ-SSCS Special Issue on High-Performance Wireline Transceiver Circuits

Wireline transceivers support the inter-package and intra-package communication between integrated circuits and are essential to scaling the performance of data centers, high-performance computing systems, and edge devices. Current high-performance electrical SERDES transceivers, which often use DAC-based transmitters and ADC-based receivers, are operating in excess of 200Gb/s for communication inside server racks and from switch chips to optical modules. However, significant design challenges include advanced energy-efficient equalization to extend channel reach, low-jitter clocking systems, and supporting alternative modulation schemes to scale to even higher data rates. Longer reach signaling is possible with optical transceivers that have traditionally been pluggable modules, but are now migrating inside the package to more efficiently meet interconnect bandwidth requirements. Intra-package communication is also increasing in importance with the rise of chiplet-based and/or 3D-stacked architectures that require energy-efficient die-to-die transceivers that achieve very high bandwidth density and are compatible with advanced packing technologies.

This special issue primarily focuses on high-performance wireline transceivers and their associated building blocks. It aims to target wireline transceiver circuits applicable across a wide spectrum of applications, such as long- and short-reach SERDES, memory/graphics interfaces, optical transceivers, and die-to-die interconnects. Original research contributions describing new integrated circuits and systems are desired, also in-depth and comprehensive review articles are welcomed.

Authors are invited to submit papers following the IEEE Open Journal of the Solid-State Circuits Society (OJ-SSCS) guidelines, within the remit of this Special Section call. Topics include (but are not limited to):

  • Novel I/O circuits and signaling methods
  • DAC/ADC/DSP-based wireline transceivers
  • Electro-optical interface circuitry for pluggable and co-packaged optics
  • High bandwidth-density die-to-die interconnects for 2.5D/3D-integrated chiplet-based systems
  • Energy-efficient analog/digital equalizers
  • Clocking techniques, PLLs, CDRs

Submission Guidelines

Please note that you need to select “High-Performance Wireline Transceiver Circuits” when you submit a paper to this Special Issue.

Deadlines

Special Section Open for Submissions: June 1, 2024
Paper Submission Deadline: August 24, 2024
First Notification: September 30, 2024
Revision Submission: October 30, 2024
Final Decision: November 15, 2024
Publication Online: December 8, 2024

Guest Editors