Special Issue on Nonvolatile Memory for Efficient Implementation of Neural/Neuromorphic Computing

CALL FOR PAPERS

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits

Special Issue on Nonvolatile Memory for Efficient Implementation of Neural/Neuromorphic Computing

 

Guest Editor - Shimeng Yu, Georgia Institute of Technology, shimeng.yu@ece.gatech.edu

Editor-in-Chief - Ian Young, Intel, ian.young@intel.com

 

Aims and Scope

In recent years, artificial intelligence based on machine/deep learning has shown significantly improved accuracy in large-scale visual/auditory recognition and classification tasks, some even surpassing human-level accuracy. In particular, deep neural networks (DNN) and their variants have proved their efficacy in a wide range of image, video, speech, and biomedical applications. To achieve incremental accuracy improvement, state-of-the-art deep learning algorithms tend to aggressively increase the depth and size of the network, which imposes ever-increasing computational capacity and storage cost in hardware. Though GPUs are the dominant technology in the training of the DNN models at the cloud, specifically designed ASIC hardware accelerators have been developed to run large-scale deep learning algorithms for inference (or even training) on-chip. This provides opportunities to bring the AI closer to the edge device for applications such as autonomous driving, machine translation, and smart wearable devices, where severe constraints exist in performance, power, and area.

In particular, the silicon CMOS ASIC designs show that limited on-chip memory capacity is the biggest bottle-neck for energy-efficient neural/neuromorphic computing, in terms of storing millions/billions of parameters and loading/communicating them to the place where computing actually occurs. Today’s ASIC designs typically utilize SRAM as the synaptic memory. Although SRAM technology has been following the CMOS scaling trend well, the SRAM density and on-chip SRAM capacity are insufficient for storing the extremely large number of parameters in deep learning algorithms. Leakage current is undesirable, and parallelism is limited due to row-by-row operation in the digital SRAM array. As an alternative hardware platform, non-volatile memory (NVM) devices have been proposed for weight storage with higher density and fast parallel analog computing with low power consumption. A special subset of NVM devices that show multilevel resistance/conductance states could naturally emulate analog synapses in the neural network. Because NVMs are potentially higher density than SRAM, they could hold most of the weights on-chip, thereby reducing or eleminating the off-chip memory access (i.e. from DRAM). The parallelism of the crossbar arrays for matrix-vector multiplication (or dot product) further enables significant acceleration of core neural computations. NVMs also offers much lower standby leakage, which could be another advantage for smart edge devices.

This special issue of the IEEE Journal on Exploratory Computational Devices and Circuits (JXCDC) aims to call for the recent research progress of the NVM based neuromorphic computing from device-level, array-level up to system-level. The interaction and co-optimization between materials/device engineering and circuit/architecture is solictated.

Topics of Interests

Prospective authors are invited to submit original works and/or extended works based on conference presentations on the topics from a wide range of NVM based neuromorphic computing. Here the NVM devices include but not limit to the following: PCM, RRAM/CBRAM, STT-MRAM (or other spintronic memory), ferroelectric based memory including FeFET or Ferroelectric Tunnel Junction (FTJ), floating-gate or charge-trap transistor, NOR and NAND Flash, etc. The following topics are solicited:

  • NVM materials/devices for neurons
  • NVM materials/devices for synapses
  • Selector materials/devices for crossbar array for analog in-memory computation
  • Array-level demonstration for analog in-memory computation
  • NVM based inference engine design including peripheral circuitry
  • NVM based training accelerator design including peripheral circuitry
  • Architectural-level design for processing-in-memory or compute-in-memory with NVM
  • Brain-inspired spiking neural networks with NVM
  • ·Hardware-aware neuromorphic learning algorithms and architectures
  • Benchmarking tools for NVM based hardware accelerator design

 

Important Dates

Open for Submission: August 1st, 2018

Submission Deadline: December 31st, 2018

First Notification: February 15th, 2019

Revision Submission: March 15th, 2019

Final Decision: April 10th, 2019

Publication Online: May 1st, 2019

 

Submission Guidelines

The IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JXCDC) IS AN OPEN ACCESS ONLY PUBLICATION: Charge for Authors: $1,350 USD per paper. Paper submissions must be done through the ScholarOne Manuscripts website:  https://mc.manuscriptcentral.com/jxcdc

 

Guidelines for papers and supplementary materials, as well as a paper template, are provided at this website (also on the next page).

Inquiries for the JxCDC Journal should be sent to:  JXCDC@IEEE.ORG

 

JxCDC is sponsored by:

  • Solid-State Circuits Society                              
  • Magnetics Society
  • Circuits & Systems Society                              
  • Nanotechnology Council          
  • Electron Devices Society
  • Council on Electronic Design Automation
  • Council on Superconductivity

PAPER FORMAT DESCRIPTION:

Papers can have 2 parts – the first part is a 4-8 page main paper (following a strict format – template available from website), and the second part is the supplementary material.  The main paper itself will just focus on describing why the work is important, the state of the prior art, the key new accomplishment(s) or results, and then what the research directions are going forward. The main paper can have an accompanying supplementary material (detailed methods) part.  The supplementary material is not mandatory, but authors are strongly encouraged to submit supplementary material, which will increase the chance of acceptance. The Supplementary material (detailed methods) will be peer reviewed along with the main paper.

 

Style guidelines for the main paper:

The main report (min. of 4, max. of 8) is written in format of a letter.  Due to their letter nature, the research must be original and must be of interest to research scientists/engineers and industry in related fields.

Abstract guidelines: The report begins with a fully referenced paragraph, ideally 200 words aimed at readers in the general area of engineering and physical sciences. The references must be up-to-date (e.g. referring to the best available materials, devices, circuits) & convey the relevance and originality of the research. This paragraph starts with a 3-4 sentence basic introduction to the problem area explaining the relevance and the issues.  This is followed by a one-sentence statement of the main conclusions (e.g. 'Here we show' or equivalent phrase); and finally, 2-3 sentences putting the main findings into general context so it is clear how the results described in the paper have moved the field forwards.

 

Body: The text of the article must be succinct and start with general audience and progressively increase the complexity for experts. The body of the main paper must provide clear context to the present work based on established industry roadmaps, figures of merit or generally accredited framework (computational throughputs, leakage power, long form Reviews of Modern physics, IEEE proceedings, Nobel lectures). To enable the comparison it is encouraged that key quantitative findings of the paper are compared in a table with current references.   Any concluding statements at the end of the article must be short since key conclusion is clearly articulated at the introduction. A repetition of the conclusions in the abstract should be avoided. Concluding statements explaining future possibilities or evolution are encouraged.

 

Style guidelines for supplementary material (methods paper):

The supplementary material is a unique format to encourage complete and clear communication of the relevant information to the experts in the area, while providing a citable source for the students for the innovations in scientific method: processing, modeling and theory. Long form derivations and code submissions are encouraged for theoretical and modeling papers. Modeling papers could for example provide all relevant data (not necessarily the code but they could) required to reproduce or validate the results. The JxCDC encourages the authors to put the experimental details such as fabrication methods, detailed characterizations, models or simulation methods (if it is a theory paper). The supplementary information therefore documents innovations in the experimental and modeling scientific methods, e.g. an innovative process technique to avoid interface effects, newly adopted differential equation solvers or innovative developments in device/circuit analysis can be included (and students/researchers will have a citable source online). Background materials that help the reader can be referenced in the supplemental material.

The supplementary material part begins with an unreferenced abstract (typically 150 words) and is divided into separate sections for introduction, results, discussion and methods. Introduction and discussion are brief and focused. The results section usually contains a general description followed by their validation. The methods section provides technical details necessary for the independent validation of the methodology, without referring to a chain of bibliographical references. The text of the supplementary material (excluding abstract, methods, references and figure legends) is limited to 6000 – 7000 words.  Articles have no more than 12 display items (figures and tables). The results and methods should be divided by topical subheadings; the discussion may contain subheadings at the author’s discretion.   If statistical testing was used to analyze the data, the methods section can contain a subsection on statistical analysis. If significant EDA tools are employed, relevant validation can be provided for the novel approach. The experimental tools and the instrumentation used must be explained in a clear schematic preferably with the models (part numbers) mentioned.

In summary, all the new contributions and accomplishments are to be summarized in the 4 to 8 page main paper. The main paper format will be such that it can be understood by not only the expert but also the non-expert (providing the context to someone unfamiliar but wanting to follow progress in the field). All experimental or simulation methods to enable reproducing/validating the results of the paper are in the supplementary material (detailed methods) part.