Abstract: Scaling a fault-tolerant quantum computer to millions of qubits required for running a practical algorithm is a daunting challenge. Silicon spin qubits are a potential technology for the scalable implementation of quantum computers thanks to their transistor-like footprint and compatibility with industrial silicon manufacturing. CMOS integrated circuits operating at cryogenic temperature can offer significantly higher system integration and enable scalability for future quantum computers. Complex System-on-Chips (SoCs) with digital, analog and RF capabilities can be integrated with sufficiently low power consumption to be compatible with the requirements of dilution refrigerators. This talk gives an overview of cryo-CMOS integrated circuits for qubit control as a solution to alleviate the cabling bottlenecks that arise with scalability, at all stages of the experimental quantum computing stack, from 4K to within the qubit chip itself at mK.
Biography: Stefano Pellerano received the Laurea Degree (summa cum laude) and the Ph.D. degree in electronics engineering from the Politecnico di Milano, Milan, Italy, in 2000 and in 2004, respectively. During his Ph.D., his activity was focused on the design of fully integrated low-power frequency synthesizers for WLAN applications. Since 2004 he has been with Intel Labs, in Hillsboro, OR. He is now Senior Principal Engineer and Lab Director leading the RF & Mixed-Signal Circuits Lab, where he drives several research activities focused at enabling radio circuit integration in deeply-scaled CMOS technologies. His main research contributions include MIMO transceivers for WiFi, digital PLLs, high-efficient digital architectures for polar and outphasing transmitters, mm-wave radio transceiver and phased-array systems, and low-power radios. In the last five years, he has also been exploring cryogenic CMOS integrated electronics for qubit control, leading to the development of “Horse Ridge”, Intel cryogenic qubit controller technology to address the interconnect bottleneck in future large-scale quantum computers. Stefano has authored or co-authored more than 70 IEEE conference and journal papers, two Nature paper, one book chapter and more than 50 patents. He was a co-recipient of IEEE International Solid-State Circuits Conference (ISSCC) 2019 Lewis Winner Award for Outstanding Paper, ISSCC 2020 Jan Van Vessem Award for Outstanding European Paper and IEEE Custom Integrated Circuits Conference (CICC) 2022 Best Paper Award. He served as a member of the ISSCC iTPC from 2014 to 2022, leading the Wireless Subcommittee from 2018 to 2022. He is serving as the Forum Chair for ISSCC since 2023. He also served as the Technical Program Chair and General Chair for the IEEE Radio Frequency Integrated Circuits (RFIC) Symposium in 2018 and 2019 respectively and he is now member of the RFIC Advisory Committee.
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