SSCS July Technical Webinar: High Performance Fractional-N PLL Design and Its Application for 5G New Radio

18 July @ 9:00 am10:30 am EDT
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Abstract: High performance fractional-N phase-locked loops (PLLs) are essential elements of any advanced electronic systems. In recent years, both analog and all-digital PLLs employing sampling or sub-sampling phase detector have gained popularity and demonstrated below 100-fs integrated jitter and superior figure-of-merit. This talk focuses on this PLL architecture and elaborates the advanced design techniques to achieve low jitter, low fractional spurs, and low power operation. Both analog circuits design and digital calibration techniques will be presented in detail. In addition, a complete LO chain design example for 5G New Radio will be illustrated in a 28/39 GHz dual-polarized 5G mm-wave cellular chipset, supporting 256-QAM and non-contiguous carrier aggregation.

Wanghua Wu received the B.Sc. degree (with honors) from Fudan University, Shanghai, China, in 2004, M.Sc. degree (cum laude) and Ph.D. degree from Delft University of Technology, The Netherlands in 2007 and 2013, respectively, all in electrical engineering. From 2013 to 2016, she was an RFIC Design Engineer in Marvell, developing high-performance frequency synthesizers for WLAN transceivers. Since 2016, she has been with Samsung Semiconductor Inc. USA. She is currently a Senior Principal Engineer and Design Manager, focusing on advanced cellular RFIC design. Her research interest is on CMOS frequency synthesis for wireless applications. She has served on the Technical Program Committee of IEEE International Solid-State Circuits Conference (ISSCC), Custom Integrated Circuits Conference (CICC), and Radio Frequency Integrated Circuits Symposium (RFIC). She served as a Distinguished Lecturer for the IEEE Solid-State Circuits Society from 2022 to 2023.

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18 July
9:00 am – 10:30 am EDT




Aeisha VanBuskirk