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Workshop Abstract: How close are we to language-to-circuit design at scale? This SSCS webinar assembles researchers advancing foundation models, agentic workflows, and open EDA. Case studies include language-to-analog synthesis, multimodal diagnosis and optimization of analog front-ends, and AI-assisted RF/mmWave design with quantitative results. The session will conclude with a brief synthesis of open research challenges, data curation, and provenance, verification, and sign-off hooks, safety/guardrails, and human-in-the-loop oversight, and propose criteria for operational readiness.
Register here: https://ieee.webex.com/weblink/register/r9d5e4ee5f06077ceff8cc10cbdaee637
Speakers:
Mehdi Saligane
Kaushik Sengupta
Mark Ren
Andrew Kahng
Chinmay Hegde
Siddharth Garg
David Pan
Speaker: Mehdi Saligane
Title: Designing Analog Circuits with Words
Abstract: Analog and mixed-signal design remains a bottleneck in IC design due to its manual, heuristic-driven nature. This talk explores how large language models (LLMs) can shift that paradigm by translating human intent, expressed in natural language, into circuit schematics, design constraints, and layout directives. We present a language-driven design workflow that integrates foundation models with open-source EDA tools, enabling rapid generation and iteration of analog blocks from high-level descriptions. By turning words into working circuits, this approach reimagines the role of the designer and opens new possibilities for accessible, automated, and creative hardware development.
Bio: Mehdi Saligane is an Assistant Professor of Electrical and Computer Engineering at Brown University and a Visiting Faculty Researcher at Google Research. He received his Ph.D. from the University of Aix-Marseille and previously held research roles at STMicroelectronics, the University of Michigan, and UC San Diego.
His work focuses on secure low-power IC design, biosensors, open-source analog/mixed-signal design automation, and custom architectures for lightweight language model accelerators. He is a founding member of the OpenROAD and OpenFASOC projects and currently chairs the IEEE SSCS Open-Source Ecosystem Technical Committee.
Dr. Saligane co-founded the SSCS Chipathon and Code-a-Chip competitions and has received the Google Cloud Research Innovators Award (2023) and the Google Research Faculty Award (2021).
Speaker: Kaushik Sengupta
Title: AI-Enabled RF/mmWave IC Design
Abstract: Traditionally, chip-scale RF system design has been in the domain of the expert, dominated by thumb rules and trial and error techniques. Designing these ICs, that form the bedrock of the wireless networks, is complex, time-consuming, requires years of expertise, and therefore, can be very expensive. Historically, the design process of RF IC design has relied on intuition based approaches with standard templates that are subsequently optimized, time-consuming parameter sweeps, or ad-hoc population-based metaheuristic optimization methods. There is no reason to believe that this approach is optimal in any sense. This talk will discuss how inverse design with AI-based approaches can open a new design space and allow rapid designs on demand. It will discuss deep-learning based modeling and generative AI approaches, that are transferrable across process design technologies, for inverse design and automated synthesis of mmWave/sub-THz circuits and antennas.
Bio: Dr. Sengupta received a B.Tech/M.Tech (dual degree) in Electronics and Electrical Communication Eng. from the Indian Institute of Technology, Kharagpur, in 2007, an M.S. in Electrical Engineering from Caltech in 2008, and a Ph.D. in Electrical Engineering from Caltech in 2012. Dr. Sengupta joined the Department of Electrical and Computer Engineering at Princeton University, Princeton, NJ, as a Faculty Member in 2013, where he is currently a Full Professor. His research interests include novel chip-scale architectures for intelligent sensing and communication for a wide range of emerging applications.
Dr. Sengupta is an IEEE Fellow. He received the DARPA Young Faculty Award in 2018, the Bell Labs Prize in 2017, the Young Investigator Program Award from the Office of Naval Research in 2017, the Prime Minister Gold Medal Award from IIT Kharagpur in 2007, the Charles Wilts Prize at Caltech for the best Electrical Engineering Ph.D. thesis in 2013, and the inaugural Young Alumni Achievement Award from IIT Kharagpur in 2018. He served as a Distinguished Lecturer for the IEEE Solid-State Circuits Society from 2019 to 2020 and for the IEEE Microwave Theory and Technology Society from 2021 to 2023. He is a recipient of the 2021 IEEE Microwave Theory and Technology Outstanding Young Engineer Award and the 2022 IEEE Solid-state Circuits New Frontier Award. He has received several best paper awards including IEEE IMS, RFIC and the Best paper of the year award from IEEE Journal of Solid-State Circuits in 2023 for the first deep-learning enabled mmWave PA design.
Speaker: Mark Ren
Title: AI for Hardware Design: From Fine-Tuned Models to Autonomous Agents
Abstract: AI is poised to revolutionize hardware design just as it has transformed software—but the path is more complex, more domain-specific, and rich with opportunity. In this talk, we explore how large language models and agentic systems are reshaping the hardware design stack, with RTL coding as a proving ground. We trace the evolution from post-training approaches that deliver high-quality Verilog through synthetic data generation and reasoning-augmented test time compute, to agentic systems capable of autonomous repair and synthesis using planning and waveform feedback. We’ll highlight frontier works in agentic RTL optimization for PPA, debug assistance for formal verification, and broader design task orchestration with dynamic self-improving agent. These examples hint at a larger future: AI agents that integrate with hardware design tools, reason over hardware-specific languages, and automate the design and verification process end-to-end. Realizing this vision will require advances in agent/model co-optimization, toolchain integration, and domain-specific language programming—but the path to autonomous hardware design has already begun.
Bio: Haoxing (Mark) Ren is the Director of Design Automation Research at NVIDIA, focusing on leveraging machine learning and GPU-accelerated tools to enhance chip design quality and productivity. He has over 25 years of industrial EDA research and development experience at IBM and NVIDIA. He holds over thirty patents and has co-authored over 100 papers and books, including a book on ML for EDA and several book chapters in EDA. He received several prestigious awards for his work, including the IBM Corporate Award and best paper awards at ISPD, DAC, TCAD, MLCAD and LAD. He serves in the organization and steering committees of international conferences such as ICCAD and ISPD and as the conference chair at ICLAD. He holds Bachelor’s and Master’s degrees from Shanghai Jiao Tong University and Rensselaer Polytechnic Institute, respectively, and earned his PhD from the University of Texas at Austin. He is a Fellow of the IEEE.
Speaker: Andrew Kahng
Title: Open-Source EDA and Agentic AI: Recent Explorations With OpenROAD
Abstract: Open-source EDA offers qualitatively different opportunities than closed-source EDA for integration with LLM-based agents and agentic AI. This talk will give a few examples from the OpenROAD context. (1) Open-source code, documentation, metrics, GitHub issues, etc. enable a rapid succession of agents, assistants, datasets and publishable demonstrations of new ML EDA ideas. (2) “ORFS-agent” (MLCAD-2025) performs LLM-driven hyperparameter tuning in OpenROAD-flow-scripts, achieving QOR comparable to BO-based autotuning with substantially fewer trials. (3) Optimization steps in the OpenROAD flow provide fertile ground for evolution of heuristics. (4) Waypoints toward an “agentic EDA R&D SWE” are now in view, spanning documentation, refactoring of code, GitHub issue creation and code implementation that can draw on research literature, and more.
[Related talks and papers on OpenROAD and ML EDA can be found at https://vlsicad.ucsd.edu]
Bio: Andrew B. Kahng is Distinguished Professor of CSE and ECE and holder of the endowed chair in high-performance computing at UC San Diego. He was visiting scientist at Cadence (1995-97) and founder/CTO at Blaze DFM (2004-06). He is coauthor of 3 books and over 500 journal and conference papers, holds 35 issued U.S. patents, and is a fellow of ACM and IEEE. He was the 2019 Ho-Am Prize laureate in Engineering. He has served as general chair of conferences such as DAC, ISPD, SLIP and MLCAD, and from 2000-2016 served as international chair/co-chair of the International Technology Roadmap for Semiconductors (ITRS) Design and System Drivers working groups. He was the principal investigator of the U.S. DARPA “OpenROAD” project (https://theopenroadproject.org/) from June 2018 to December 2023, and until August 2023 served as principal investigator and director of “TILOS” (https://tilos.ai/), a U.S. NSF AI Research Institute.
Speaker: Chinmay Hegde
Title: Do LLMs Dream of Electric Chips?
Abstract: LLMs are on their way to becoming indispensable tools for software engineers, but are yet to reach the same level of adoption in hardware design languages (HDL). To pave the way for a robust ecosystem of HDL-specialized LLMs to flourish, it is imperative to develop high quality, open-source datasets and benchmarks. In this talk, I will first introduce VeriThoughts, the first large-scale annotated Verilog dataset that contains paired prompts/questions, reasoning traces, and quality labels for over 20,000 Verilog modules. I will discuss how formal verification plays a key role in the design and construction of this dataset. I will then detail our efforts to building VeriThoughts-7B and VeriThoughts-14, which (to our knowledge) are the first hardware-focused fully open-source thinking LLMs. Time permitting, I wiill talk about my past work on LiveBench, a dynamically updating benchmark for measuring reasoning capabilities in frontier AI models, and suggest an framework for community-driven benchmarking of LLMs for chip design.
Bio: Chinmay Hegde is an Associate Professor at NYU, jointly appointed with the CSE and ECE Departments. His research focuses on foundational aspects of machine learning (such as reliability, robustness, efficiency, and privacy). He also works on diverse applications of AI in engineering domains ranging from computational imaging, hardware design, plant science, and cybersecurity. He is a recipient of the National Science Foundation’s CAREER and CRII awards, two teaching awards, and best paper awards at ICML, SPARS, and MMLS.
Speaker: Siddharth Garg
Title: Foundation Models for Hardware Design
Abstract: In this talk, I will present our work over the past several years on developing foundation models for hardware design, spanning both digital and analog domains. This is a particularly challenging problem because much of the data in the hardware and semiconductor industry is locked behind proprietary walls—often protected as intellectual property by chip design companies—and therefore unavailable in the public domain. To address these challenges, we have explored three complementary directions. First, by scraping available data from repositories like GitHub, we have trained state-of-art LLMs finetuned for Verilog code generation. Second, we show that these models also produce meaningful embeddings of Verilog code that enable early-stage RTL-level predictions of performance and area, providing valuable guidance for design-time optimization. Finally, we descrive Masala-CHAI, the largest known dataset of SPICE netlists along with rich metadata, and demonstrate their utility for training and evaluating analog design models. Together, these efforts bring us closer to building foundation models that can significantly accelerate and democratize hardware design.
Bio: Siddharth Garg is currently the Institute Associate Professor of ECE at NYU Tandon, where he leads the EnSuRe Research group (https://wp.nyu.edu/ensure_group/). Prior to that he was in Assistant Professor also in ECE from 2014-2020, and an Assistant Professor of ECE at the Unversity of Waterloo from 2010-2014. His research interests are in machine learning, cyber-security and computer hardware design. He received his Ph.D. degree in Electrical and Computer Engineering from Carnegie Mellon University in 2009, and a B.Tech. degree in Electrical Engineering from the Indian Institute of Technology Madras. In 2016, Siddharth was listed in Popular Science Magazine’s annual list of “Brilliant 10” researchers. Siddharth has received the NSF CAREER Award (2015), and paper awards/nominations at the ACM TODAES’23, IEEE TCAD’19, DATE’23, IEEE Symposium on Security and Privacy (S&P) 2016 and USENIX Security Symposium 2013. Siddharth also received the Angel G. Jordan Award from ECE department of Carnegie Mellon University for outstanding thesis contributions and service to the community. He serves on the technical program committee of several top conferences in the area of computer engineering and computer hardware, and has served as a reviewer for several IEEE and ACM journals.
Speaker: David Pan
Title: Automated Analog Design via Multi-Modal LLMs: Generation, Diagnosis, and Optimization
Abstract: Analog front-end design remains heavily reliant on expert intuitions and iterative simulations. Building on our earlier AnalogCoder, we present AnalogCoder-Pro, a unified multi-modal LLM framework for analog circuit generation, diagnosis, and optimization. It introduces an autonomous repair workflow using simulation errors and waveform images, and builds a reusable circuit library to accelerate complex designs. From target specs, it generates topologies, extracts key parameters, and applies Bayesian optimization for device sizing—enabling end-to-end design. Experiments on 30 tasks across 15 circuit types show strong performance. While analog data remains limited, continued LLM advances (e.g., GPT-4.1) continue to improve results. AnalogCoder-Pro demonstrates the promise of multi-modal AI in driving the next generation of intelligent analog design tools.
Bio: David Z. Pan is the Silicon Labs Endowed Chair Professor at the Department of Electrical and Computer Engineering, The University of Texas at Austin. His research interests include design automation for digital/analog/mixed-signal/RF ICs and emerging technologies, synergistic AI/IC co-optimizations, design and technology/system co-optimizations, etc. He has published over 520 refereed journal/conference papers and 10 US patents. He has served in many editorial boards and conference committees, e.g., as DAC 2024 TPC Chair and ICCAD 2019 General Chair. He has received many awards, including SRC Technical Excellence Award, 21 Best Paper Awards from premier EDA/chips venues, DAC Top 10 Author Award in Fifth Decade, among others. He has graduated 55 PhD students and postdocs who are now holding key academic and industry positions. He is a Fellow of ACM, IEEE, and SPIE.