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May Technical Webinar: The Promise of 2-D materials for Scaled Digital and Analog Applications, Presented By: Devin Verreck

Date
2023-05-04
Time
9:00 AM ET
Location
Webinar - Online
Contact
Aeisha VanBuskirk – a.vanbuskirk@ieee.org
Web site
https://ieee.webex.com/weblink/register/rbc95fe09f54075870fc316f905db1ae8
Sponsorship
Sponsor
Presenter
Devin Verreck
Description
Abstract: The scaling roadmap of silicon channel MOSFETs is reaching its fundamental limits. In this seminar, we discuss the potential of 2-D materials to break through this barrier thanks to their sub-nm thickness. We go from material to device to circuit level simulation assessment, highlighting benefits for scaled digital, analog and back-end-of-line applications. We conclude with an evaluation of the experimental state-of-the-art and the remaining challenges.

Bio: Devin Verreck received the MSc degree in Nanoscience and Nanotechnology in 2012 and the PhD degree in Electrical Engineering in 2017 from the KU Leuven summa cum laude with congratulations of the board of examiners. The topic of his thesis was the quantum modeling of tunnel field-effect transistors. He is now a principal researcher in the TCAD team at imec, where he develops models for the optimization of 2-D material FETs and 3-D NAND flash memories.