SSCS Webinar Series - Professional Development, Networking, and Career Growth
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The Race for Efficiency in Short Reach Wireline - Presented By: Davide Tonietto
- 11:00 AM EST
- Webinar - Online
- Aeisha VanBuskirk – firstname.lastname@example.org
- Davide Tonietto
- Biography: Davide Tonietto received the Laurea Degree in Electrical Engineering from Pavia University, Italy in 1996. He has worked in several IC companies as analog IC designer and technical manager. He holds more than 20 US patents in the areas of Analog and Mixed Signal IC design and wireline communication systems and authored several papers on the subjects. He joined Huawei Canada in 2011 where he is Huawei Fellow and Senior Director of Hisilicon Serial Link Team (HiLink) with teams in Canada and China. His research interests are in the area of SerDes architecture, design, optimization, testing and reliability for 100Gbps and beyond for both copper and optical applications.
Abstract: Information explosion and its exponentially increasing demands on data traffic and processing are pushing a rapid and diverse evolution in short reach wireline interconnect technologies. In the background of this race, CMOS technology is not providing the usual node over node boost in performance to help SerDes designers cope with higher bandwidth and data rates. Breakthroughs in high speed electrical interconnect and new approaches in optical interconnect, such SiPho, NPO (near package optics) and CPO (co-packaged optics) promise improved performance, energy efficiency and density. How are these new technologies going to address the ever more complex energy efficiency and density problems facing our industry?