Digital Frequency Synthesis: Journey towards Spectral Purity, Ultra-Low Power and Millimeter-Wave Operation, Presented by R. Bogdan Staszewski
- 2014-10-20 - 2014-10-20
- 12:00pm EST
- Webinar - Online
- Mike Markowycz – email@example.com
Attendees of this IEEE SSCS webinar have the opportunity to earn Continuing Education Certificates! To request your certificate complete the form by clicking HERE. *Please note: Your certificate request will be completed within 7-10 business days.
Frequency synthesizers are key components of RF and mixed-signal system-on-chip (SoC) solutions. As CMOS processes scale down, raw transistor performance and power consumption dramatically improve, but difficulties arise in implementing traditional phase-locked loop (PLL) architectures. Starting with the 130nm CMOS node, digitally intensive and all-digital PLLs have emerged as alternatives to the traditional charge-pump PLLs. They consist of a digitally controlled oscillator (DCO) to generate a multi-GHz output clock and a time-to-digital converter (TDC) to digitize the generated output phase. The loop filter between the DCO and TDC is built of logic gates. A major misconception the digital frequency synthesizers have always been facing is that they somehow produce more noise and spurs while consuming more power. This seminar gives an overview of the digital frequency synthesis journey, from its humble beginnings in the year 2000 to the current 28nm node where it outperforms its traditional analog counterparts in almost all aspects, including high spectral purity performance, ultra-low power, and mm-wave operation.
R. Bogdan Staszewski received BSEE (summa cum laude), MSEE and PhD from University of Texas at Dallas, USA, in 1991, 1992 and 2002, respectively. From 1991 to 1995 he was with Alcatel in Richardson, Texas. He joined Texas Instruments in Dallas, Texas in 1995. In 1999 he co-started a Digital RF Processor (DRP) group in TI with a mission to invent new digitally-intensive approaches to traditional RF functions. Dr. Staszewski served as a CTO of the DRP group between 2007 and 2009. In July 2009 he joined Delft University of Technology in the Netherlands where he is currently a part-time Full Professor. Since Sept. 2014 he is a Professor at University College Dublin (UCD) in Ireland. He has co-authored one book, four book chapters, 170 journal and conference publications, and holds 120 issued US patents. His research interests include nanoscale CMOS architectures and circuits for frequency synthesizers, transmitters and receivers. He is an IEEE Fellow and a recipient of IEEE Circuits and Systems Industrial Pioneer Award (http://ieee-cas.org/about/awards/industrial-pioneer-award).
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