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Scaling SerDes Beyond 100Gb/s in Advanced CMOS Technologies - Presented by Frank O'Mahony

Date
2022-03-17
Time
10:00 AM ET
Location
Webinar - Online
Contact
Abira Altvater – abira.altvater@ieee.org
Description

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ABSTRACT - Over the past two decades, high-speed wireline data rates have doubled every three-to-four years to keep pace with aggregate system bandwidth requirements. Communication standards for networking and storage, like Ethernet and OIF-CEI, tend to be the first to shift to higher data rates in order to support bandwidth density requirements for datacenters, supercomputers, telecom and AI hardware. Today, SerDes IPs up to 116Gb/s are reaching maturity and pathfinding for SerDes transceivers capable of sending data over 200Gb/s is well underway.

Maintaining this exponential bandwidth trend while staying within acceptable die area and system thermal limits has clearly benefitted from continuous CMOS process technology scaling. However, the rate of bandwidth increase and required improvements in energy efficiency have exceeded the benefits of process technology scaling alone. SerDes system and circuit architecture have had to evolve and improve to fill this gap. In addition, the benefits of scaled CMOS process technology come with challenges for transistor and interconnect reliability and the parasitics for scaled geometries. Increasing data rates and relatively constant link distances have gradually required some longer-reach copper interconnects to be replaced by optical channels. But, for now, electrical signaling continues to be the primary way that data gets on and off of the chips, packages and boards at the heart of high-bandwidth systems.

This presentation will start by providing an introduction to SerDes, including standards, basic signal integrity and link equalization and clocking architecture. Next it will describe system and circuit design techniques that have extended per-lane bandwidth to 100Gb/s, including PAM-4 modulation and ADC/DSP-based receivers, along with the benefits and challenges of designing high-speed transceivers in scaled CMOS technologies. Finally it will show some recent design and measurement results for the next leap in SerDes data rates up to 224Gb/s.


BIO- Frank leads the I/O Circuit Technology group within Advanced Design at Intel in Hillsboro, Oregon. He is a Fellow and Director of I/O Design Enablement at Intel. His team coordinates circuit-process co-design for wireline I/O at Intel. They also design and test the first I/Os on each new CMOS process technology. From 2003 until 2011 he was a member of the Signaling Research group in Intel Labs. His work at Intel spans high-speed and low-power transceivers, clock generation and distribution, equalization, analog design in scaled CMOS and on-die measurement techniques.

Frank received the BS, MS, and PhD degrees in electrical engineering from Stanford University in 1997, 2000 and 2004, respectively. He has published over 45 papers in peer-reviewed conferences and journals. He has received the ISSCC Jack Kilby Award, IEEE Journal on Solid-State Circuits Best Paper Award and TCAS Darlington Best Paper Award. Frank has been on the ISSCC Technical Program Committee since 2012 including five years as the Wireline Subcommittee chair. He currently serves as the ISSCC 2022 Forums Chair. He is a Senior Member of the IEEE and served as an IEEE Distinguished Lecturer. Frank currently chairs the IEEE SSCS Distinguished Lecturer Program.

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