Past Webinars

< Back to events

Resonant Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor with Visvesh Sathe

Date
2012-05-16
Location
Webinar - Online
Contact
Mike Kelly, SSCS Exec. Dir – m.p.kelly@ieee.org
Description

Attendees of this IEEE SSCS webinar have the opportunity to earn Continuing Education Certificates!  To request your certificate complete the form by clicking HERE.  *Please note: Your certificate request will be completed within 7-10 business days. 

This presentation is an extended encore of a paper recently delivered at the 2012 International Solid-State Circuits Conference (ISSCC) in San Francisco, CA.. AMD's 4+ GHz x86–64 core codenamed “Piledriver” employs resonant clocking to reduce clock distribution power up to 24% while maintaining a low clock-skew target. To support testability and robust operation at the wide range of operating frequencies required of a commercial processor, the clock system operates in two modes: direct-drive and resonant. Leveraging favorable factors such as the availability of two thick top-level metals, high operating frequency, clock-load density, and the existing clock-design methodology, the resonant clock mode was designed to enable both reduced average power dissipation and improved peak-power-constrained performance, with minimal area impact. This work represents a volume production-enabled implementation of resonant clock technology, and is plan of record for mid-2012 product offerings.

Event Recording