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Continuous-Time Pipelined ADC for Wide-Bandwidth Wireless Receivers

Date
2020-11-20
Time
11AM-12:30PM
Location
Webinar - Online
Contact
Abira Altvater – abira.altvater@ieee.org
Presenter
Hajime Shabata
Description

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ABSTRACT

The design space of analog-to-digital converters (ADC) can be classified by two orthogonal axes – one representing the different ADC architectures such as SAR, pipeline, and ΔΣ; the other mapping the underlying circuits as discrete-time and continuous-time configurations.  For ΔΣ ADCs, both discrete- and continuous-time design topologies have been explored extensively. With continuous-time implementations excelling in power efficiency and bandwidth, continuous-time ΔΣ ADCs have been widely used in a variety of applications including wireless communication systems. One then might ask – if continuous-time ΔΣ ADCs offer multiple key benefits over discrete-time counterparts, does the same rationale apply to other ADC architectures such as pipelined ADCs? This webinar attempts to answer this question. We first present how a continuous-time pipelined ADC can be derived from a discrete-time equivalent. We then cover the pros and cons of the continuous-time pipelined ADC against discrete-time pipelined and continuous-time ΔΣ ADCs.  We also present the implementation examples in 28nm and 16nm CMOS technologies. We will conclude the talk with a discussion of future research directions.

BIOGRAPHY

Hajime Shibata (S’99–M’02–SM’19) received B.E. and M.E. degrees in electrical engineering from the University of Electro-Communications, Tokyo, Japan, in 1997 and 1999, respectively, and the Ph.D. degree from Tokyo Institute of Technology in 2002. Since 2002, he has been with Analog Devices, where he has been working on continuous-time ΔΣ and continuous-time pipelined analog-to-digital converter designs. Dr. Shibata was a co-recipient of the Beatrice Winner Award at ISSCC 2006. He has served as an Associate Editor of IEEE Transactions on Circuits and Systems II from 2017 to 2019.

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