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Phase-Locked Loops: System Perspectives Tailored for IC Designers, Presented by Woogeun Rhee

Date
2017-11-30
Time
11:00 AM ET
Location
Webinar - Online
Contact
Abira Sengupta – abira.sengupta@ieee.org
Description
Abstract: A phase-locked loop is a key building block in wireline and wireless systems. In the wireline systems, low-jitter clock generation and versatile clock-and-data recovery circuits are critical in high data rate I/O links. In the wireless systems, the fractional-N frequency synthesizer plays a critical role in modern transceivers not only as a local oscillator but also as a phase modulator with direct digital modulation. However, the traditional PLL in advanced CMOS technology suffers from poor scalability, loop parameter variability and leakage current problems. Accordingly, diversified PLL architectures and circuit techniques have been proposed in consideration of performance, power and cost, thus making it difficult for circuit designers to choose the right design solution. In this talk, system perspectives and application aspects of the PLL which are useful for IC designers will be discussed.
 
 
Bio: Woogeun Rhee received the B.S. degree in electronics engineering from Seoul National University, Seoul, Korea, in 1991, the M.S. degree in electrical engineering from the University of California, Los Angeles, in 1993, and the Ph.D. degree in electrical and computer engineering from the University of Illinois, Urbana-Champaign, in 2001. From 1997 to 2001, he was with Conexant Systems, Newport Beach, CA, where he was a Principal Engineer and developed low-power, low-cost fractional-N synthesizers. From 2001 to 2006, he was with IBM Thomas J. Watson Research Center, Yorktown Heights, NY and worked on clocking area for high-speed I/O serial links, including low-jitter phase-locked loops, clock-and-data recovery circuits, and on-chip testability circuits. In August 2006, he joined the faculty as an Associate Professor at the Institute of Microelectronics, Tsinghua University, Beijing, China, and became a Professor in December 2011. His current research interests include short-range low-power radios for next generation wireless systems and clock/frequency generation circuits for wireline and wireless communications. He holds 23 U.S. patents. Dr. Rhee is currently an IEEE Distinguished Lecturer of the Solid-State Circuits Society (2016-2017) and serves as an Associate Editor for IEEE JSSC. He has been an Associate Editor for IEEE TCAS-II (2008-2009) and a Guest Editor for IEEE JSSC Special Issue in November 2012 and November 2013. He has served as a member of several IEEE conferences, including ISSCC (2012-2016), CICC, and A-SSCC.

 

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