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"Energy-efficient circuit technologies for sub-14nm microprocessors and SoCs: challenges and opportunities" by Ram Krishnamurthy

Date
2016-07-13
Time
12:00 PM EST
Location
Webinar - Online
Contact
Abira Sengupta – abira.sengupta@ieee.org
Description

Attendees of this IEEE SSCS webinar have the opportunity to earn Continuing Education Certificates!  To request your certificate complete the form by clicking HERE.  *Please note: Your certificate request will be completed within 7-10 business days. 

 

Abstract: This seminar presents some of the prominent barriers to designing energy-efficient circuits in the sub-14nm technology regime and outlines new paradigm shifts necessary in next-generation multi-core microprocessors and systems-on-chip. Emerging trends and key challenges in sub-14nm design are outlined, including (i) device and on-chip interconnect technology projections, (ii) performance, leakage and voltage scalability, (iii) special-purpose hardware accelerators and reconfigurable co-processors for compute-intensive signal processing algorithms, (iv) fine-grain power management with integrated voltage regulators, and (v) resilient circuit design to enable robust variation-tolerant operation. Energy-efficient arithmetic and logic circuit techniques, static/dynamic supply scaling, on-die interconnect fabric circuits, ultra-low-voltage and near-threshold logic and memory circuit techniques, and multi-supply/multi-clock domain design for switching and leakage energy reduction are described. Special purpose hardware accelerators and data-path building blocks for enabling high GOPS/Watt on specialized DSP tasks such as encryption, graphics and media processing are presented. Power efficient optimization of microprocessors to span a wide operating range across high performance servers to ultra-mobile SoCs, dynamic on-the fly configurability and adaptation, and circuit techniques for active/standby-mode leakage reduction with robust low-voltage operability are reviewed. Specific chip design examples and case studies supported by silicon measurements and trade-offs will be discussed.

 

RamKrishnamurthyIntelPhoto

Bio: Ram K. Krishnamurthy received the B.E. degree in electrical engineering from Regional Engineering College, Trichy, India, in 1993, and the Ph.D. degree in electrical and computer engineering from Carnegie Mellon University, Pittsburgh, PA, in 1998. Since 1998, he has been with Intel Corporation’s Circuits Research Labs in Hillsboro, Oregon, where he is currently a Senior Principal Engineer and heads the High-performance and Low-voltage Circuits research group. He is responsible for research in high performance, energy efficient and low voltage circuits for microprocessors and SoCs. He holds 104 issued patents with over 50 patents pending and has published three book chapters and 150 conference and journal papers. Dr. Krishnamurthy serves on the Technical Advisory Board of Semiconductor Research Corporation and has served as Guest Editor of the IEEE journal of solid-state circuits and on the technical program committees of ISSCC, CICC, and SOCC conferences. He served as the Technical Program Chair/General Chair for the 2005/2006 IEEE International Systems-on-Chip Conference and presently serves on the conference’s steering committee. He has received two Intel Achievement Awards, in 2004 and 2008, for the development of novel arithmetic circuit technologies and hardware encryption accelerators. In 2012, he received the ISSCC distinguished technical paper award and ESSCIRC best paper award. He is a Fellow of IEEE and distinguished lecturer of IEEE solid-state circuits society.

 

Event Recording