DL Event Calendar
DL Event Calendar
SSCS Macau - Kenichi Okada
- University of Macau
- IEEE Region 10 (Asia and Pacific)
- Pui-In Mak – email@example.com
Abstract: In this presentation, some design techniques for fractional-N digital PLL will be introduced to improve both jitter and power consumption for low-power wireless applications. A highly-linear and low-power DTC and TDC will be presented as well as system-level optimization. An isolated constant-slope DTC realizes 10bit 0.1mW operation with 26MHz reference clock, and sub-ps INL is achieved. The DTC-based AD-PLL achieves FoM of -246dB with 0.98mW power consumption and -56dBc worst-case fractional spur. For further power saving, duty-cycled FLL, sub-sampling/sampling switching, charge-recycling DTC, and transformer-based DCO for impedance peaking will be also explained, which achieves 0.265mw power consumption with FoM of -237dB at 2.4GHz. Finally, a DPLL-based ADC and a BLE transceiver using DPLL will be introduced.
Bio: Kenichi Okada is an Associate Professor of Electrical and Electronic Engineering at Tokyo Institute of Technology. He received the B.E., M.E., and Ph.D. degrees in Communications and Computer Engineering from Kyoto University, Kyoto, Japan, in 1998, 2000, and 2003, respectively. From 2000 to 2003, he was a Research Fellow of the Japan Society for the Promotion of Science in Kyoto University. From 2003 to 2007, he was an Assistant Professor at the Precision and Intelligence Laboratory, Tokyo Institute of Technology, Yokohama, Japan. Since 2007, he has been an Associate Professor in the Department of Physical Electronics and then the Department of Electrical and Electronic Engineering, Tokyo Institute of Technology, Tokyo, Japan. He has authored or co-authored more than 400 journal and conference papers. His current research interests include millimeter-wave CMOS wireless transceivers for 20/28/39/60/77/79/100/300GHz for WiGig, 5G, satellite and future wireless system, digital PLL, synthesizable PLL, atomic clock, and ultra-low-power wireless transceivers for Bluetooth Low-Energy, and Sub-GHz applications.
Prof. Okada is a member of the IEEE, the Institute of Electronics, Information and Communication Engineers (IEICE), the Information Processing Society of Japan (IPSJ), and the Japan Society of Applied Physics (JSAP). He received the Ericsson Young Scientist Award in 2004, the A-SSCC Outstanding Design Award in 2006 and 2011, the ASP-DAC Special Feature Award in 2011 and Best Design Award in 2014 and 2015, JSPS Prize in 2014, Suematsu Yasuharu Award in 2015, MEXT Prizes for Science and Technology in 2017, and more than 40 other international and domestic awards. He is/was a member of the technical program committees of ISSCC, VLSI Circuits, and ESSCIRC, and he also is/was Guest Editors and an Associate Editor of IEEE Journal of Solid-State Circuits.