DL Event Calendar

DL Event Calendar

< Back to events

SSCS/CAS Central Texas - Jae-Yoon Sim

Date
2019-02-25
Time
TBD
Location
EER 0.806/808, University of Texas at Austin
Region
IEEE Region 5 (Southwestern USA)
Contact
Jaydeep P. Kulkarni – jaydeep@austin.utexas.edu
Description

Talk Title: Design of synthesizable digital PLL

Abstract: There have been constant efforts to develop digital-intensive implementation of analog building blocks. The phase-locked loop (PLL), as a key analog block, has been one of the most actively researched topics in this area. The time-to-digital converter (TDC) plays a major role in determination of the achievable performance of digital PLL, and the requirements on TDC becomes even worse in fractional-N PLL. This presentation reviews principles of digital PLL with noise and jitter analyses. The talk also introduces implementation examples of recently proposed synthesizable fractional-N PLLs.