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SSCS/CAS Uttar Pradesh - Vivek De

Date
2018-11-03
Time
10:30 AM
Location
Indian Institute of Technology-Roorkee
Region
IEEE Region 10 (Asia and Pacific)
Contact
Brajesh Kumar Kaushik – bkk23fec@iitr.ac.in
Description
Talk Title: Energy Efficient Computing in Nanoscale CMOS
Abstract: Future computing systems spanning exascale supercomputers to wearable devices demand orders of magnitude improvements in energy efficiency while providing desired performance. The system-on-chip (SoC) designs need to span a wide range of performance and power across diverse platforms and workloads. The designs must achieve robust near-threshold-voltage (NTV) operation in nanoscale CMOS  process while supporting a wide voltage-frequency operating range with  minimal impact on die cost. We will discuss circuit and design technologies to overcome the challenges posed by device parameter variations, supply noises, temperature excursions, aging-induced degradations, workload and activity changes, and reliability considerations. The major pillars of energy-efficient SoC designs are: (1) circuit/design optimizations for fine-grain multi-voltage & wide dynamic range, (2) fine-grain on-die power delivery & management, (3) dynamic adaptation & reconfiguration, (4) dynamic on-die error detection & correction, and (5) efficient interconnects.