Distinguished Lecturer Roster

"Everyone has been impressed by the vibrant and informative presentations of these renowned distinguished lecturers and valued the unique opportunity of having intimate technical discussions and exchanging ideas with such internationally recognized experts."

- Shahriar Mirabbasi, Chapter Chair of Vancouver SSCS, CPMT, and CESOC Joint Chapter, May 2015.

Terms through 31 December 2022

Mike Shuo-Wei  Chen portrait
Mike Shuo-Wei Chen
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Terms through 31 December 2022

Mike Shuo-Wei Chen is a professor in Electrical Engineering Department at University of Southern California (USC) and holds the Colleen and Roberto Padovani Early Career Chair position. He received the B.S. degree from National Taiwan University, Taipei, Taiwan, in 1998 and the M.S. and Ph.D. degrees from University of California, Berkeley, in 2002 and 2006, all in electrical engineering.

As a graduate student, he proposed and demonstrated the asynchronous SAR ADC architecture, which has been adopted in industry today for low-power high-speed analog-to-digital conversion products. After joining USC in 2011, he leads an analog mixed-signal circuit group, focusing on high-speed low-power data converters, frequency synthesizers, RF/mm-wave transceiver designs, analog circuit design automation, bio-inspired computing, non-uniformly sampled circuits and systems. From 2006 to 2010, he worked on mixed-signal and RF circuits for various wireless communication products at Atheros Communications (now Qualcomm).

Dr. Chen was the recipient of Qualcomm Faculty Award in 2019, NSF Faculty Early Career Development (CAREER) Award, DARPA Young Faculty Award (YFA) both in 2014, Analog Devices Outstanding Student Award for recognition in IC design in 2006 and UC Regents’ Fellowship at Berkeley in 2000.  He also achieved an honorable mention in the Asian Pacific Mathematics Olympiad, 1994. Dr. Chen has been serving as an associate editor of the IEEE Solid-State Circuits Letters (SSC-L), IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), as well as a TPC member in IEEE Solid-State Circuits Society conferences, notably the IEEE International Solid-State Circuits Conference (ISSCC), IEEE Symposium on VLSI Circuits (VLSIC), and IEEE Custom Integrated Circuits Conference (CICC).

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PresentationAbstract
Asynchronous SAR ADC: Past, Present and Beyond Read Abstract
High-Performance Digital-to-Analog Converter Design: A Path towards Digital Transmitter Read Abstract
New Opportunities in Non-Uniform Sampling Read Abstract
Trend in Digital PLL Design and New Opportunities in Spur Cancellation Read Abstract
Qinwen Fan portrait
Qinwen Fan
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Terms through 31 December 2022

Qinwen Fan received her PhD degree from Delft University of Technology in 2013. From October 2012 to May 2015, she worked at Maxim Integrated in Delft, The Netherlands. From June 2015 to January 2017, she worked at Mellanox (currently known as Nvidia) in Delft, the Netherlands. Since 2017, she rejoined the Delft University of Technology and is currently an Assistant professor in the electronics and instrumentation laboratory.

Her current research interests include precision analog, current sensing, class D audio amplifiers, DC-DC converters and autonomous wireless sensor nodes.

Dr. Fan serves as an associate editor of Open Journal of the Solid-State Circuits Society (OJ-SSCS), a TPC member of International Solid-State Circuits Conference (ISSCC), and a TPC member of European Solid-state circuits conference (ESSCIRC).

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PresentationAbstract
High switching frequency class D audio amplifiers Read Abstract
Precision Amplifiers: a road towards perfection Read Abstract
Brian Ginsburg portrait
Brian Ginsburg
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Terms through 31 December 2022
Brian Ginsburg received his S.B., M.Eng., and Ph.D. degrees from the Massachusetts Institute of Technology.   He joined Texas Instruments, Dallas, Texas in 2007 working in its wireless terminals business unit and TI’s Kilby Labs.  Now, he is a Distinguished Member of Technical Staff and the systems manager of TI’s radar business.  He has served on the technical program committee for the International Solid-State Circuits Symposium and is the Symposium Co-Chair of the 2021 Symposium on VLSI Circuits.
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PresentationAbstract
Digitally Enhanced mm-Wave Radars Read Abstract
mm-Wave Imaging for Automotive and Beyond Read Abstract
Danielle Griffith portrait
Danielle Griffith
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Terms through 31 December 2022
Texas Instruments

Danielle Griffith received the B.S.E.E. and M.Eng. degrees from the Massachusetts Institute of Technology, Cambridge in 1996 and 1997, respectively. She joined Motorola in Tempe, AZ in 1997 and worked in the area of RF circuit design.  In 2003, she joined Texas Instruments in Dallas, Texas and is a Fellow in the Connectivity business unit.  She develops circuits and techniques for reducing cost, power consumption, and circuit board area for low power wireless connectivity products.  Her current focus areas are architectures for efficient wireless systems, low power oscillators and MEMS circuitry.  She has published >50 papers, most of them in IEEE journals or conferences.   She has written a book chapter titled “Synchronization Clocks for Ultra-Low Power Wireless Networks” which was published by Springer as a part of the book “Ultra-Low-Power Short-Range Radios”.  Danielle holds 19 issued US patents and has given multiple university and IEEE conference tutorial and workshop sessions.  She was a member of the Technical Program Committees for the IEEE RFIC Symposium for conferences years 2014 and 2015, the IEEE International Solid-State Circuits Conference for conference years 2015-2019, and the VLSI Symposium starting in 2019. 

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PresentationAbstract
Frequency Generation for the Internet of Things Read Abstract
Precision BAW oscillators for low power, high performance applications Read Abstract
Radio Architectures and Circuits for Low Power Wide Area Networks Read Abstract
Towards Zero: Power Consumption Trends in Low Data Rate Wireless Connectivity Products Read Abstract
Jaydeep Kulkarni portrait
Jaydeep Kulkarni
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Terms through 31 December 2022

(S’03–M’09–SM’15) Jaydeep Kulkarni received B.E. degree from University of Pune, India in 2002, M. Tech degree from Indian Institute of Science (IISc) in 2004 and Ph.D. degree from Purdue University in 2009. During 2009-2017, he worked as a Research Scientist at Intel Circuit Research Lab in Hillsboro, OR. Currently, he is an assistant professor in the department of electrical and computer engineering at the University of Texas at Austin and a fellow of Silicon Labs Chair in electrical engineering and a fellow of AMD chair in computer engineering. 

Dr. Kulkarni has filed 36 patents, published 2 book chapters, and 85 papers in refereed journals and conferences. His research is focused on machine learning hardware accelerators, in-memory computing, DTCO for emerging nano-devices, heterogeneous and 3D integrated circuits, hardware security, and cryogenic computing. He received 2004 best M. Tech student award from IISc Bangalore, 2008 Intel Foundation Ph.D. fellowship award, 2010 Purdue school of ECE outstanding doctoral dissertation award, 2015 IEEE Transactions on VLSI systems best paper award, 2015 SRC outstanding industrial liaison award, 2018, 2019 Micron Foundation Faculty Awards, and 2020 Intel Rising Star Faculty Award. He has participated in technical program committees of CICC, A-SSCC, DAC, ICCAD, ISLPED, and AICAS conferences. He currently serves as an associate editor for IEEE Solid State Circuit Letters and IEEE Transactions on VLSI Systems. He is also serving as a distinguished lecturer for the IEEE Solid State Circuit Society and as the chair of IEEE Solid State Circuits Society and Circuits and Systems Society central Texas joint chapter. He is a senior member of IEEE and National Academy of Inventors.

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PresentationAbstract
Compute-in-Memory Designs: Trends and Prospects Read Abstract
High performance embedded memory design in advanced FinFET technologies Read Abstract
Noriyuki  Miura portrait
Noriyuki Miura
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Terms through 31 December 2022

Noriyuki Miura received the B.S., M.S., and Ph.D. degrees in electrical engineering all from Keio University, Yokohama, Japan, in 2003, 2005, and 2007 respectively. From 2005 to 2008, he was a JSPS Research Fellow and since 2007 an Assistant Professor with Keio University, where he developed wireless interconnect technology for 3D integration. In 2012, he moved to Kobe University, Kobe, Japan, and became a Professor at Osaka University, Suita, Japan in 2020. Also, he was concurrently appointed as a JST PRESTO researcher, and now working on hardware security/safety and next-generation heterogeneous computing systems. Dr. Miura is currently serving as a Technical Program Committee (TPC) Member for A-SSCC and Symposium on VLSI Circuits. He served as the TPC Vice Chair of 2015 A-SSCC. He was a recipient of the Top ISSCC Paper Contributors 2004-2013, the IACR CHES Best Paper Award in 2014.

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PresentationAbstract
Integrated Security Interface Against Cyber-Physical Attacks Read Abstract
Smart Metal Passives Read Abstract
Alyosha Christopher Molnar portrait
Alyosha Christopher Molnar
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Terms through 31 December 2022

Alyosha Molnar received his B.S. in engineering from Swarthmore College in 1997, and M.S. (2003) and Ph.D. (2007) in electrical engineering from the University of California, Berkeley. From 1998 to 2002, he was with the RFIC Group at Conexant Systems, Inc., Newport Beach, CA, where he co-led the development of their first-generation GSM direct conversion receiver. In graduate school he worked on one of the first sub-milliwatt radios for “smart dust”, before spending several years in a neuroscience lab studying the biological circuits that underlie early image processing in the mammalian retina.  In 2007, he became a faculty member with the School of Electrical and Computer Engineering at Cornell University.  His research interests span RF and mm-wave integrated circuits for flexible wireless systems, novel image sensors and associated image processing, neuroscience and neural interface systems and circuits, and microscale autonomous systems.  He is a recipient of many teaching and research awards including the NSF CAREER award, DARPA Young Faculty Award, and the ISSCC Lewis Winner award.

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PresentationAbstract
Analog at the Extremes: Wireless Signals from Watts to Nanowatts Read Abstract
Flexible Radio Front-Ends For A Crowded, Dynamic Spectrum Read Abstract
Integrated Optoelectronic Sensors For Biology Read Abstract
N-path Passive Mixers: Simple Circuits, Surprising Capabilities Read Abstract
Arijit Raychowdhury portrait
Arijit Raychowdhury
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Terms through 31 December 2022

Arijit Raychowdhury is the Motorola Foundation Professor in the School of Electrical and Computer Engineering at the Georgia Institute of Technology. From 2013 to July 2019, he was an Associate Professor and held the ON Semiconductor Junior Professorship with the department. His industry experience includes five years as a Staff Scientist with the Circuits Research Lab, Intel Corporation, and two years as an Analog Circuit Researcher with Texas Instruments Inc. Dr. Raychowdhury’s research interests include low-power digital and mixed-signal circuit design and exploring interactions of circuits with device technologies. Dr. Raychowdhury has authored over 200 articles in journals and refereed conferences and holds more than 26 U.S. and international patents. Dr. Raychowdhury and his group have also received numerous awards and fellowships. Dr. Raychowdhury was the recipient of the Qualcomm Faculty Award in 2020, the IEEE/ACM Innovator under 40 Award in 2018, the NSF CISE Research Initiation Initiative Award (CRII), in 2015, Intel Faculty Award in 2015, the Intel Labs Technical Contribution Award, in 2011, the Dimitris N. Chorafas Award for outstanding doctoral research, in 2007. His students have also won several prestigious fellowships and 13 best paper awards over the years. He is a Senior Member of IEEE and currently serves on the technical program committees of several IEEE Conferences.

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PresentationAbstract
All-Digital and Digital-Assisted Integrated Low-Dropout Regulators (LDOs) for Fine-Grained Spatiotemporal Power Management of Digital Load Circuits Read Abstract
Bits and Brains: Ultra-low Power, Neuro-inspired Edge-AI for Autonomous Systems Read Abstract
Chris Rudell portrait
Chris Rudell
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Terms through 31 December 2022

Jacques “Chris”tophe Rudell received degrees in electrical engineering from the University of Michigan (BS), and UC Berkeley (MS, PhD). After finish his PhD, he worked for several years as an RF IC designer at Berkana Wireless (now Qualcomm), and Intel Corporation.  In January 2009, he joined the faculty at the University of Washington, Seattle, where he is now an Associate Professor of Electrical and Computer Engineering. He is also a member of the Center for Neural Technology (CNT) and serves as the co-director of the Center for Design of Analog-Digital Integrated Circuits (CDADIC).

While a PhD student at UC Berkeley, Dr. Rudell received the Demetri Angelakos Memorial Achievement Award, a citation given to one student per year by the EECS department. He has twice been co-recipient of the best paper awards at the IEEE International Solid-State Circuits Conference, the first of which was the 1998 Jack Kilby Award, followed by the 2001 Lewis Winner Award. He received the 2008 ISSCC best evening session award, and best student paper awards at the 2011 and 2015 RFIC Symposium. Chris is the recipient of the National Science Foundation (NSF) CAREER Award. Dr. Rudell served on the ISSCC technical program committee (2003-2010), and on the IEEE Radio Frequency Integrated Circuits (RFIC) Symposium steering committee (2002-2013), where he was the 2013 General Chair. He was an Associate Editor for the IEEE Journal of Solid-State Circuits (2009-2015). At present, he serves on the technical program committees of the IEEE European Solid-State Circuits Conference (ESSCirC) and the IEEE Custom Integrated Circuits Conference (CICC).

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PresentationAbstract
On-Chip Self-Interference Mitigation for Integrated Systems Read Abstract
Seung-Tak Ryu portrait
Seung-Tak Ryu
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Terms through 31 December 2022
Seung-Tak Ryu is a professor in school of electrical engineering at KAIST. He Received the B.S. degree in electrical engineering from Kyungpook National University, Korea, in 1997, and the M.S. and Ph.D. degrees from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1999 and 2004, respectively. From 2001 to 2002, he was with the University of California, San Diego, CA, USA, as a Visiting Researcher. Before joining KAIST as a faculty member, he was with Samsung Electronics, Yongin, Korea, where he was involved in mixed-signal IP design. He served on the technical program committees (TPC) of the ISSCC and served as a guest editor of the IEEE journal of solid-state circuits. He currently serves as a member of TPCs of ASSCC, CICC, and ESSCIRC. He also serves as an associate editor of the IEEE solid-state circuits letters.
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PresentationAbstract
Architectural Evolution of Power-efficient ADCs Assisted by SAR ADCs Read Abstract
Bringing Back Pipelined ADCs in the Era of SAR ADCs Read Abstract
Visvesh S. Sathe  portrait
Visvesh S. Sathe
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Terms through 31 December 2022
Visvesh S. Sathe received the B.Tech. degree from the Indian Institute of Technology, Bombay and the M.S. and Ph.D. degrees from the University of Michigan, Ann Arbor. He is currently an Associate Professor of Electrical and Computer Engineering at the University of Washington where he leads the Processing Systems Lab (PSyLab), focused on research associated with energy-efficient computing and implantable electronics. Prior to joining the University of Washington, he served as a Member of Technical Staff in the Low-Power Advanced Development Group at AMD, where his research focused on inventing and implementing circuit, clocking and supply mitigation technologies in next-generation microprocessors. These technologies include high-speed digital circuits, adaptive clocking for supply noise mitigation and resonant clocking. His current research interests include implementation of run-time hardware control and optimization in digital and mixed-signal systems over a range of applications. He is the recipient of an NSF Career award in 2019 and more recently, the Intel outstanding researcher award in 2021. He serves on the technical program committee of the IEEE Custom Integrated Circuits Conference
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PresentationAbstract
Exploiting Run-time Computing to Build Better Circuits...for Computing Read Abstract
Solving the SoC Supply Noise Problem through Adaptive Clocking: Past, Present, and Future Read Abstract
Sudip Shekhar portrait
Sudip Shekhar
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Terms through 31 December 2022

Sudip Shekhar received his B.Tech. degree from the Indian Institute of Technology, Kharagpur, and the Ph.D. degree from the University of Washington, Seattle.

From 2008 to 2013, he was with the Circuits Research Laboratory, Intel Corporation, Hillsboro, OR, USA, where he worked on high-speed I/O architectures. He is now an Associate Professor of Electrical and Computer Engineering with The University of British Columbia, Vancouver. His current research interests include circuits for electrical and optical interfaces, frequency synthesizers, and wireless transceivers.

Dr. Shekhar was a recipient of the Young Alumni Achiever Award by IIT Kharagpur in 2019, the IEEE Transactions on Circuit and Systems Darlington Best Paper Award in 2010 and a co-recipient of IEEE Radio-Frequency IC Symposium Student Paper Award in 2015. He serves on the technical program committee of IEEE International Solid-State Circuits Conference (ISSCC), Custom Integrated Circuits Conference (CICC) and Optical Interconnects (OI) Conference.

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PresentationAbstract
Coherent Silicon Photonic Links Read Abstract
Frequency Synthesis Type One Read Abstract
In-Band Full-Duplex Radios: Present and Future Read Abstract
Scaling up silicon photonic-based accelerators: Challenges and opportunities Read Abstract
Silicon: The playground for photons and electrons Read Abstract
Nan Sun portrait
Nan Sun
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Terms through 31 December 2022

Nan Sun is Professor with Tsinghua University. He was Assistant and then tenured Associate Professor with the University of Texas at Austin. He received B.S. degree from Tsinghua University in 2006, and Ph.D. degree from Harvard University in 2010. Dr. Sun received the NSF Career Award in 2013, and the inaugural IEEE SSCS New Frontier Award in 2020. He has published over 160 papers at premier journal and conferences, including 29 JSSC papers and 47 ISSCC/VLSI/CICC papers. He serves on the Technical Program Committee of CICC and ASSCC. He served as an Associate Editor of TCAS-I, and a Guest Editor of JSSC. He also serves as Distinguished Lecturer for both IEEE Circuits-and-Systems Society and IEEE Solid-State Circuits Society.

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PresentationAbstract
Break the kT/C Noise Limit Read Abstract
Compressive Sensing Techniques for Low-Power Sensor Design Read Abstract
The Floating Inverter Amplifier Read Abstract
When SAR meets Delta Sigma Read Abstract
Filip Tavernier portrait
Filip Tavernier
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Terms through 31 December 2022
Filip Tavernier obtained the M.Sc. degree in Electrical Engineering and the Ph.D. degree in Engineering Science from KU Leuven, Leuven, Belgium, in 2005 and 2011, respectively. During 2011-2014, he was Senior Fellow in the microelectronics group at the European Organization for Nuclear Research (CERN) in Geneva, Switzerland. He was involved in chip designs for the upgrade program of the Large Hadron Collider (LHC) experiments. In 2014, he rejoined KU Leuven at the Department of Electrical Engineering (ESAT-MICAS). As of October 2015, he has been a 
professor within the same department. His main research interests include circuits for optical communication, data converters, DC-DC converters, and chips for cryogenic environments. 
Filip is a member of the technical program committees of ESSCIRC, CICC, and SBCCI. He has been SSC-L Guest Editor and is the current SSCS Webinar Chair.
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PresentationAbstract
Exploring the Speed – Accuracy – Power Limits of Nyquist ADC Architectures Read Abstract
The Step Size – Input Range – Efficiency Trade-Off in SC DC-DC Converters Read Abstract
Using CMOS for Optical Communication Read Abstract

Terms through 31 December 2023

Jane Gu portrait
Jane Gu
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Terms through 31 December 2023
University of California, Davis

Dr. Qun Jane Gu has received the Ph.D. from University of California, Los Angeles in 2007. After a couple years of industry experience, she started her academia career in 2010 at the University of Florida. Since 2012, she has been with the University of California, Davis, where she is currently a professor. Dr. Jane Gu’s group is passionate in high performance RF, mm-wave and THz integrated circuits and systems and its broad applications. The works from her group have won nine best paper awards from international conferences. She has received 2013 NSF CAREER award, 2015 UC Davis Outstanding Junior Faculty Award, 2017 and 2018 Qualcomm Faculty Award, and 2019 UC Davis Chancellor Fellow. She is a TPC member of solid-state circuits conferences RFIC, CICC and ISSCC.

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PresentationAbstract
THz Interconnect, Complement to Electrical and Optical Interconnects Read Abstract
Robert Henderson portrait
Robert Henderson
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Terms through 31 December 2023
University of Edinburgh

Robert Henderson (M’82, SM’14, F’21) is a Professor of Electronic Imaging in the School of Engineering at the University of Edinburgh. He obtained his PhD in 1990 from the University of Glasgow. From 1991, he was a research engineer at the Swiss Centre for Microelectronics, Neuchatel, Switzerland. In 1996, he was appointed senior VLSI engineer at VLSI Vision Ltd, Edinburgh, UK where he worked on the world’s first single chip video camera. From 2000, as principal VLSI engineer in STMicroelectronics Imaging Division he developed image sensors for mobile phone applications. He joined University of Edinburgh in 2005, designing the first SPAD image sensors in nanometer CMOS technologies in the MegaFrame and SPADnet EU projects. This research activity led to the first volume SPAD time-of-flight products in 2013 in the form of STMicroelectronics Flightsense series which perform an autofocus assist function in more than 150 different smartphone models, recently passing the 1 billion module milestone. He benefits from a long term research partnership with STMicroelectronics in which he explores medical, scientific and high speed imaging applications of SPAD technology. In 2014, he was awarded a prestigious ERC advanced fellowship. He is a Fellow of the Royal Society of Edinburgh.

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PresentationAbstract
3D Stacked CMOS SPAD Image Sensors Read Abstract
Biomedical and Scientific Imaging with CMOS SPAD Sensors Read Abstract
Direct Time of Flight LIDAR with CMOS SPAD Arrays Read Abstract
Jaeha Kim portrait
Jaeha Kim
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Terms through 31 December 2023
Seoul National University
Jaeha Kim is currently Professor at Seoul National University (SNU), Seoul, Korea and his research interests include low-power mixed-signal circuits and their design methodologies. He founded Scientific Analog, Inc. in 2015, developing EDA tools for analog/mixed-signal modeling and simulation in SystemVerilog. He received B.S. degree in electrical engineering from Seoul National University in 1997, and M.S. and Ph.D. degrees in electrical engineering from Stanford University in 1999 and 2003, respectively. Prior to joining SNU, Prof. Kim was with Stanford University as Acting Assistant Professor, with Rambus, Inc. as Principal Engineer, and with Inter-university Semiconductor Research Center (ISRC) at SNU as Post-doctoral Researcher. Prof. Kim is a recipient of the Takuo Sugano award for outstanding far-east paper at 2005 ISSCC and is cited as Top 100 Technology Leader of Korea in 2020 by the National Academy of Engineering of Korea.

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PresentationAbstract
Advanced Modeling and Simulation of State-of-the-Art High-Speed I/O Interfaces Read Abstract
Efficient Simulation of Analog/Mixed-Signal Circuits in SystemVerilog with Auto-Generated Models Read Abstract
Introduction to Silicon Photonics Systems and Their Modeling Read Abstract
Tony Tae-Hyoung Kim portrait
Tony Tae-Hyoung Kim
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Terms through 31 December 2023
Nanyang Technological University

Tony Tae-Hyoung Kim (Senior Member, IEEE) received the B.S. and M.S. degrees in electrical engineering from Korea University, Seoul, South Korea, in 1999 and 2001, respectively, and the Ph.D. degree in electrical and computer engineering from the University of Minnesota, Minneapolis, MN, USA, in 2009. From 2001 to 2005, he was with Samsung Electronics, Hwasung, South Korea. In 2009, he joined Nanyang Technological University, Singapore, where he is currently an Associate Professor.

He has published over 190 papers in journals and conferences and holds 20 U.S. and Korean patents registered. His current research interests include computing-in-memory for machine learning, ultra-low power circuits and systems for smart edge computing, low-power and high-performance digital, mixed-mode, and memory circuit design, variation-tolerant circuits and systems, and emerging memory circuits for neural networks.

Dr. Kim received IEEE ISSCC Student Travel Grant Award in 2022 and 2019, Best Paper Award (Gold Prize) in IEEE/IEIE ICCE-Asia2021, Korean Federation of Science and Technology (KOFST) Award in 2021, Best Demo Award at APCCAS2016, Low Power Design Contest Award at ISLPED2016, Best Paper Awards at 2014 and 2011 ISOCC, AMD/CICC Student Scholarship Award at IEEE CICC2008, DAC/ISSCC Student Design Contest Award in 2008, Samsung Humantech Thesis Award in 2008, 2001, and 1999, and ETRI Journal Paper of the Year Award in 2005. He was the Chair of the IEEE Solid-State Circuits Society Singapore Chapter in 2015-2016 and is Chair-Elect/Secretary of the IEEE Circuits and Systems Society VSATC. He has served on numerous IEEE conferences as a Committee Member. He serves as a Corresponding Guest Editor for the IEEE JOURNAL on EMERGING and SELECTED TOPICS in CIRCUITS and SYSTEMS (JETCAS), a Guest Editor for the IEEE TRANSACTIONS on BIOMEDICAL CIRCUITS and SYSTEMS (TBioCAS), an Associate Editor for the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS and IEEE ACCESS.

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PresentationAbstract
Design of computing-in-memory: Analog vs. Digital Read Abstract
Minimum-energy-driven embedded memory design for IoT applications Read Abstract
Tiny ML accelerator design for IoT applications: Challenges and Trends Read Abstract
Nagendra  Krishnapura portrait
Nagendra Krishnapura
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Terms through 31 December 2023
Indian Institute of Technology, Madras
Nagendra Krishnapura obtained his BTech from the Indian Institute of Technology, Madras, India, and his PhD from Columbia University, New York. He has worked as an analog design engineer at Celight, Multilink, and Vitesse semiconductor. He has taught analog circuit design courses at Columbia University as an adjunct faculty. He is currently a professor at the Indian Institute of Technology, Madras. His interests are analog and RF circuit design and analog signal processing.

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PresentationAbstract
Maximizing the Data Rate of an Inductively Coupled Chip-to-Chip Link by Resetting the Channel State Variables Read Abstract
Multi-channel Analog-to-Digital Conversion Using Delta-Sigma Modulators Without Reset Read Abstract
Widely Tuning-Range VCOs Using Multi-Mode Resonators Read Abstract
Hanh-Phuc Le portrait
Hanh-Phuc Le
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Terms through 31 December 2023
University of California, San Diego

Dr. Hanh-Phuc Le is an Assistant Professor of ECE at the University of California San Diego and a co-Director of the Power Management Integration Center, an NSF IUCRC center. He received the Ph.D. degree from UC Berkeley (2013), M.S. from KAIST, Korea (2006), and B.S. from Hanoi University of Science and Technology in Vietnam (2003), all in Electrical Engineering. In 2012, he co-founded and served as the CTO at Lion Semiconductor until October 2015. The company was acquired by Cirrus Logic in 2021. He was with the University of Colorado Boulder from 2016 to 2019, before joining the ECE department at UC San Diego. He held R&D positions at Oracle, Intel, Rambus, JDA Tech in Korea and the Vietnam Academy of Science and Technology (VAST) in Vietnam. His current research interests include miniaturized/on-die power conversions, large conversion ratios, smart power delivery and control for high performance IT systems, data centers, telecommunication, robots, automotive, mobile, wearable, and IoT applications. 

 

Dr. Le received a 2021 NSF CAREER Award, a 2012-2013 IEEE Solid-State Circuits Society Pre-doctoral Achievement Award, and UC Berkeley's 2013 Sevin Rosen Funds Award for Innovation. He authored three book chapters, over fifty journal and conference papers with one best paper award, recognized in various topics in the area of integrated power electronics. He is an inventor with 21 U.S. patents (11 granted and 10 pending). He serves as an associate editor of the IEEE Journal of Emerging and Selected Topics in Power Electronics (JESTPE), TPC Chair/co-chair for the International Workshop on Power Supply On Chip (PwrSoC 2018, 2020), and Chair of the Power Management and Outreach Subcommittees at the IEEE Custom Integrated Circuits Conference  (2020, 2021), and Vice Chair of the Energy Conversion Congress and Exposition (ECCE) 2021. He is also the Chair of the IEEE Power Electronics Society Technical Committee on Power Components, Integration, and Power ICs (IEEE PELS TC2). Dr. Le is an IEEE Senior Member. 
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PresentationAbstract
Gate Driver Circuits for Multi-Level Power Converters Read Abstract
Integrated Power Converter - A Good Design Flow and Useful Techniques Read Abstract
Next-Generation Circuit Architectures for Power-Supply on Chip (PwrSoC) Read Abstract
Yoonmyung  Lee portrait
Yoonmyung Lee
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Terms through 31 December 2023

Yoonmyung Lee received a B.S. degree in Electronic and Electrical Engineering from the Pohang University of Science and Technology (POSTECH), Pohang, Korea, in 2004, and his M.S. and Ph.D. degree in Electrical Engineering from the University of Michigan, Ann Arbor, in 2008 and 2012, respectively. From 2012 to 2015, Dr. Lee was with the University of Michigan as a research faculty member. In 2015, he joined Sungkyunkwan University, Suwon, Korea, where he is now an Associate Professor.

Dr. Lee is a recipient of Samsung Scholarship in 2005 and Intel Ph.D. fellowship in 2011. He has been serving as a Technical Program Committee member for Asian Solid-State Circuits Conference (A-SSCC) since 2017, and Custom Integrated Circuits Conference (CICC) since 2020. He also has been serving as an associate editor for IEEE Transactions on Very Large Scale Integration (VLSI) Systems since 2019. His research interests include energy-efficient integrated circuits design for low-power high-performance integrated systems and millimeter-scale wireless sensor systems.

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PresentationAbstract
Securing IoT Systems with Cost-Effective Physically Unclonable Functions Read Abstract
Tackling Dynamic Power with Low Power and Variation-Tolerant Flip-Flops Read Abstract
Yan Lu portrait
Yan Lu
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Terms through 31 December 2023
University of Macau, China

Yan Lu received his BEng and MSc degrees from South China University of Technology, Guangzhou, China, in 2006 and 2009, respectively, and the PhD degree from the Hong Kong University of Science and Technology (HKUST), Hong Kong, China, in 2013.

In 2014, he joined the State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China, where he is currently an Associate Professor. He has authored/coauthored more than 100 peer-reviewed technical papers and one book entitled CMOS Integrated Circuit Design for Wireless Power Transfer (Springer), and edited one book entitled Selected Topics in Power, RF, and Mixed-Signal ICs (River Publishers). His research interests include wireless power transfer circuits and systems, high density power converters, integrated voltage regulators, and energy-efficient analog circuits.

Dr. Lu was a recipient/co-recipient of the NSFC Excellent Young Scientist Fund (HK-Macau) in 2021, the Macao Science and Technology Award second prizes in both 2018 and 2020, the IEEE Solid-State Circuits Society Pre-Doctoral Achievement Award 2013–2014, the IEEE CAS Society Outstanding Young Author Award in 2017, and the ISSCC 2017 Takuo Sugano Award for Outstanding Far-East Paper. He has served as a Guest Editor for the IEEE TCAS-I in 2019 and the IEEE TCAS-II from 2018 to 2019, a Young Editor of the Journal of Semiconductors since 2021. He is serving as a TPC Member for ISSCC and CICC.

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PresentationAbstract
Hybrid Topologies of Device-to-Device Bi-directional Wireless Power Transceiver Read Abstract
Integrated Voltage Regulators for Fine-Grained Power Delivery Read Abstract
Danilo Manstretta portrait
Danilo Manstretta
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Terms through 31 December 2023
University of Pavia

Danilo Manstretta (Member, IEEE) received the MS degree (summa cum laude) and the Ph.D. degree in electrical engineering and computer science from the University of Pavia, Pavia, Italy, in 1998 and 2002, respectively.

From 2001 to 2003 he was with Agere Systems as a Member of Technical Staff, working on WLAN transceivers and linear power amplifiers for base stations.

From 2003 to 2005 he was with Broadcom Corporation, Irvine, CA, working on RF tuners for TV applications.

In 2005 he joined the University of Pavia, where he is now Associate Professor. His research interests are in the field of analog, RF, optical and millimeter-wave integrated circuit design.

Dr. Manstretta has been member of the Steering Committee of the IEEE Radio Frequency Integrated Circuits (RFIC) Symposium since 2017. He was TPC member for the same conference from 2006 to 2021 and he is the TPC co-chair in 2022. Since 2022 he is member of the TPC of ESSCIRC. He was Guest Editor of the IEEE Journal of Solid-State Circuits May 2017 Special Section dedicated to the 2016 RFIC Symposium and Guest Editor of the IEEE Transactions on Microwave Theory and Techniques June 2018 Mini Special Issue dedicated to the 2017 RFIC Symposium. He was co-recipient of the 2003 IEEE Journal of Solid-State Circuits Best Paper Award.

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PresentationAbstract
Trans-impedance amplifiers design: from ultra-low-power analog to ultra-wideband RF Read Abstract
Carolina Mora Lopez  portrait
Carolina Mora Lopez
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Terms through 31 December 2023
imec

Carolina Mora Lopez received her Ph.D. degree in Electrical Engineering in 2012 from the KU Leuven, Belgium, in collaboration with imec, Belgium. From 2012 to 2018, she worked at imec as a researcher and analog designer focused on interfaces for neural-sensing applications. During this time, she was the lead analog designer and project leader of the Neuropixels development project which resulted in the conception and fabrication of the Neuropixels 1.0 and 2.0 neural probes. She is currently the principal scientist and team leader of the Circuits & Systems for Neural Interfaces team at imec, which develops circuits and technologies for electrophysiology, neuroprosthetics and BMI. Her research interests include analog and mixed-signal circuit design for sensor, bioelectronic and neural interfaces. Carolina is a senior IEEE member and serves on the technical program committee of the ISSC conference, ISSCC SRP, VLSI circuits symposium, and ESSCIRC conference.

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PresentationAbstract
Circuits and technologies for implantable biomedical devices Read Abstract
Matteo Perenzoni  portrait
Matteo Perenzoni
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Terms through 31 December 2023
Sony Europe Technology Development Centre

Matteo Perenzoni (M’09, SM’19) graduated in electronics engineering from the University of Padua, Italy, and received the PhD in Physics from University of Ferrara, Italy.

In 2002, he collaborated with the University of Padua on mixed-signal integrated circuit design for channel decoding. In 2004, he joined the Fondazione Bruno Kessler (FBK), Trento, Italy, as a Researcher working at the Integrated Radiation and Image Sensors (IRIS) Research Unit. Meanwhile, he also taught courses on electronics and sensors at the Master and Doctorate School, University of Trento, Trento. In 2014, he was a Visiting Research Scientist with the THz Sensing Group, Microelectronics Department, TU Delft, The Netherlands. From 2017 to 2021 he led the IRIS Research Unit at FBK, working in the field of radiation and image sensors using custom and CMOS technologies. Since 2021 he is with the Sony Europe Technology Development Centre in Trento, Italy, leading the analog IC design team. His research interests include advanced CMOS image sensors with a focus on single-photon detection, THz image sensors, and optimization of analog integrated circuits.

Dr. Perenzoni has been a member of the Technical Program Committee of the European Solid-State Circuit Conference (ESSCIRC), from 2015 to 2021 and of the International Solid-State Circuit Conference (ISSCC) from 2018 to 2022.

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PresentationAbstract
Imaging in CMOS technologies using single-photon avalanche diodes Read Abstract
One more dimension: 3D range imaging with time-of-flight Read Abstract
Sensing beyond visible light with Terahertz radiation Read Abstract
Yvain  Thonnart  portrait
Yvain Thonnart
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Terms through 31 December 2023
CEA-List

Yvain Thonnart received the MS degree from Ecole Polytechnique and an engineering diploma from Telecom Paris, France in 2005. He then joined the Technological Research Division of CEA, the French French Alternative Energies and Atomic Energy Commission, within the CEA-Leti institute until 2019, then within the CEA-List institute. He has led the development of several large research projects for on-chip communications, focusing on the maturation of novel concepts towards industrial adoption, such as communication between multiple voltage and frequency domains, 3D-stacked circuits, and optical on-chip interconnects, leading to more than 70 publications and 10 patents. He is now senior expert on communication and synchronization in systems on chip, and scientific advisor for the mixed-signal design lab. His main research interests include asynchronous logic, networks on chip, physical implementation, emerging technologies integration such as photonics, cryoelectronics and interposers. He is currently serving in the technical program committee of the ISSCC.

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PresentationAbstract
On-chip communication : from architectures to circuits Read Abstract
Rangharajan  Venkatesan portrait
Rangharajan Venkatesan
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Terms through 31 December 2023
NVIDIA

Rangharajan Venkatesan is a Senior Research Scientist in the ASIC & VLSI Research group in NVIDIA. He received the B.Tech. degree in Electronics and Communication Engineering from the Indian Institute of Technology,  Roorkee in 2009 and the Ph.D. degree in Electrical and Computer Engineering from Purdue University in August 2014. His research interests are in the areas of low-power VLSI design and computer architecture with particular focus in deep learning accelerators, high-level synthesis, and spintronic memories. He has received Best Paper Awards for his work on deep learning accelerators from IEEE/ACM Symposium on Microarchitecture (MICRO) and Journal of Solid-State Circuits (JSSC). His work on spintronic memory design was recognized with the Best Paper Award at the International Symposium on Low Power Electronics and Design (ISLPED), and Best paper nomination at the Design, Automation and Test in Europe (DATE). His paper titled, “MACACO: Modeling and Analysis of Circuits for Approximate Computing”, received the IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Ten Year Retrospective Most Influential Paper Award in 2021. He is a member of the technical program committees of several leading IEEE/ACM conferences including ISSCC, DAC, MICRO, and ISLPED.

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PresentationAbstract
Pushing the Energy-efficiency of Deep Learning Accelerators with Hardware-Software Co-design Read Abstract
Scalable Deep Neural Network Hardware with Multi-Chip Modules Read Abstract
David Wentzloff portrait
David Wentzloff
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Terms through 31 December 2023
University of Michigan

David Wentzloff received a BS in Electrical Engineering from the University of Michigan, and Ph.D. in EE from MIT. Since, 2007 he has been with the University of Michigan, where he is currently an Associate Professor of Electrical Engineering and Computer Science. His research focuses on RF integrated circuits, with an emphasis on ultra-low power design. In 2012, he co-founded Everactive, a fabless semiconductor company developing ultra-low power wireless SoCs, where he is currently the co-CTO.

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PresentationAbstract
FASoC: Fully-Autonomous SoC Synthesis Read Abstract
Ultra-Low Power Receivers for IoT Applications Read Abstract
Wanghua Wu portrait
Wanghua Wu
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Terms through 31 December 2023
Samsung Semiconductor Inc. USA

Wanghua Wu (M’07) received the B.Sc. degree (with honors) from Fudan University, Shanghai, China, in 2004, M.Sc. degree (cum laude) and Ph.D. degree from Delft University of Technology, The Netherlands in 2007 and 2013, respectively, all in electrical engineering.

From 2013 to 2016, she was an RFIC Design Engineer in Marvell, developing high-performance frequency synthesizers for WLAN transceivers. Since 2016, she has been with Samsung Semiconductor Inc. USA. She is currently a Senior Manager and Principal Engineer, focusing on advanced cellular RFIC design. Her research interest is on CMOS frequency synthesis for wireless applications.

She is currently served as the Technical Program Committee member of IEEE International Solid-State Circuits Conference (ISSCC), Custom Integrated Circuits Conference (CICC), and Radio Frequency Integrated Circuits Symposium (RFIC).

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PresentationAbstract
Low-Jitter LO Frequency Synthesis for 5G mm-wave Transceiver Read Abstract
Recent Trends and Advances in High Performance Fractional-N PLL Design Read Abstract