None of the inventors of the transistor could probably imagine 75 years ago that chips have now invaded our daily life leading to an unprecedent impact on our society. Over these 75 years of semiconductor development, the performances have been increased and the cost reduced by many orders of magnitude which is unique in the industry history. This enabled new applications that were simply not possible before, among which the Internet of Things (IoT). Today, the IoT is probably the application which poses the most stringent requirements in terms of energy consumption and has hence become the primary driver for low-power. The design of low-power analog and RF circuits in advanced technologies at low-voltage has become ever more challenging. Because of voltage scaling, the traditional strong inversion region is progressively disappearing, pushing operating points into moderate or even weak inversion. In this presentation we will introduce the inversion coefficient IC as the main transistor design parameter which can cover the entire range of operating points from weak via moderate to strong inversion. We will show how it can help exploring the design space using various figures-of-merit (FoM) and find the right trade-offs between typically power, speed, linearity and noise.

Collaboration between companies and universities has been critical to building the integrated circuit industry that we know today. The symbiotic connection between companies and universities is critical to IC technology development and for preparing a proficient and work-ready workforce. As we grapple with the shortage of IC’s worldwide, this partnership has once again become critical. In this talk, highlights from conversations with a few dozen company engineering leaders and university faculty points to some of the challenges faced in this collaboration while emphasizing the tremendous synergies and opportunities. University faculty and students often seek to collaborate with companies in research, internships, and bringing real-world perspectives to the classroom. This exposure can be very beneficial to students and enhances the relevance of university research. Companies are motivated to engage with universities so that they have a prepared workforce and can tap into the intellectual creativity of the research. On the surface, it looks like a match made in heaven. The goal of this talk is to plant seeds for how universities and companies can chart a path that creates the win-win as we seek to overcome the current IC shortages.

This lecture will cover basics of public-key encryption, and example design optimization of elliptic-curve based encryption algorithm, including pairing operations, and its security measures. Then extend design optimization on lattice-based encryption algorithms including post quantum crypto-algorithm, and fully homomorphic encryption algorithm.

The discovery, then invention, of the transistor sits almost exactly midway between Ferdinand Braun's discovery of solid-state rectification in 1874 and the modern era of gigascale ICs. As with other epoch-shattering inventions, the story of the transistor isn't quite as neatly linear as some recountings might suggest. Very few newly-minted EEs have ever heard of a point-contact transistor, and even those few are unlikely to know that these devices often exhibited a negative current gain (beta). This talk will answer questions such as, "What was an alloy-junction transistor? What were surface-barrier transistors? What was the hometaxial process? What happened to germanium devices? How can you build a single-transistor, non-switching voltage inverter?" Retracing some of the steps of the pioneers generates important insights into the nature of innovation, as well as a much deeper appreciation of the role of chance. As the end of lithographic scaling seemingly positions us on the threshold of a major technological discontinuity, it is perhaps helpful to study the story of the previous one.

75 years after the creation of the transistor, the entire world recognizes semiconductor technology as one of the most important assets of human civilization's advancement. This lecture describes how the number of integrated transistors has been increased from LSI to VLSI (Millions) to today’s GSI (Billions) and soon to be TSI (Trillions) in next decade. An analytical model is proposed to describe the MOSFET evolution starting from the Planar Structure (named as Silicon Age 1.0 or Si1.0), then to Si2.0 using a 3D transistor. Then, a Heterogeneous Integration of Technology (termed HI Roadmap by IEEE) by integrating dice, and chiplets within one package to realize Smart-Microsystems (Si3.0). Following this comes Si4.0, which integrates Silicon and Non-Silicon devices together and optimizes both Monolithic and Heterogeneous Integration together to achieve more functions/values in one Package/Module. The transistor is continuously improved toward Feature Size～1.0nm, Ioff～1pA, and Tera-bits on a die. The critical challenge is how to reduce the cost-per-bit in the migration of technology node, which is the most difficult task demanded by the Real Moore’s Law Economy. Due to the extremely large computing capabilities derived from semiconductor integration and development, more and more pervasive intelligence Microsystems will be created to advance human civilization to an Intelligence^N Era.

This is really a love story. Not about antique technology, but about a wild period of jaw-dropping creativity that was the golden era of the bipolar transistor. The almost magical properties of the BJT and the diverse set of problems it was called on to solve are nothing short of astonishing: a DAC that automatically corrects for transistor sizing, an LDO loop invariant to PVT, a multiplier made from one transistor, and an equation for synthesizing…well, almost anything. No, this is not just nostalgia. It is a lesson in creative thinking. It is a blueprint for the next golden era of circuit magic.

After the invention of the transistor in 1947, vacuum tubes were replaced by these little components, which did not break when you dropped them and which did not have to be heated before use. By putting several transistors on a single chip, they could be produced in larger numbers at a lower cost. Over the years, the circuits built with transistors changed from analog to digital operation, while even today, analog circuits remain crucial to interface with the physical world. The transistors have scaled from centimeter size to a few nanometers today, resulting in chips with tens of billions of transistors on them, available at a price that almost every person on the planet can afford them. This talk will address the changes the transistor experienced during 75 years of downsizing and how circuit design has changed over the years: from a handful of artistically combined bipolar transistors to high-complexity digital systems. But even in these modern digital chips, we need to interface with the real world and analog behavior is still needed. This opens the door for new circuits exploiting the benefits of modern CMOS technology, if possible with an artistic twist.

The first papers about integrated PLLs appeared in late sixties, the circuits were of course designed in BJT technology, often including some external components. This block today is still a key element in communication circuits. Actually, in recent years thanks to MOS scaling, it is also one of the building block on which the designers’ creativity was most allow to run free. As a matter of fact the use of scaled MOS technology allowed the implementation of so-called digitally-intensive PLLs, in which several calibrations, for instance based on least-mean square technique running in background, improve most of the PLL performance, a solution that couldn't even be dreamed of, at the time of the first integrated PLLs. However, the designer must still have a strong knowledge of the key issues of analog IC design to exploit technology scaling, from this standpoint the situation is unchanged. The fundamental limits, mostly noise and power, then matching, non linearity, and also quantization in “digital” PLL, are still there. The talk will discuss these issues taking as an example some recent implementation of digitally-intensive PLLs, evidencing the advantages of this approach but also the limitations and trade-off.

While CMOS transistors came to dominate integrated circuits, some other transistor types such as the bipolar junction transistor (BJT); its variant, the super-beta BJT; the junction gate field-effect transistor (JFET) and laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOS) continue to thrive in specific applications. The talk will re-visit the discovery of these transistor types, their operating principles and key characteristics and look at circuit examples that benefit from these characteristics. We will look how these transistors have eluded extinction despite their larger feature sizes and process complexities and how they have evolved in modern technologies.

Deep learning is influencing not only the technology itself but also our everyday lives. In this presentation, the status of AI and DNN SoCs will be reviewed from the viewpoint of the mobile and edge AIs, and the evolution of DNN accelerators. Especially, low power NPU and reconfigurable NPU will be introduced for mobile, embedded, and IoT platforms. In addition, Dynamically Reconfigurable Processor architecture will be explained in detail with the real chip measurement results, such as human emotion recognition for intelligent HCI. Moreover, the on-chip training, which will be the next wave over the current AI revolution, and low power training processors will be explained with algorithms and hardware co-optimization methods for personalized and privacy protected AI applications. NPU examples such as Real-time training, GAN, DRL, Depth Camera and 3D Rendering examples will be introduced for the many exciting low-power and high-performance applications in Gaming, AR/VR, Intelligent Robotics, Drones, Autonomous Driving, Security Camera, Health Monitoring and IoT. Lastly, the future of NPU such as PIM (Processing In Memory) and Spike Neural Network Chips which are realized with custom memories including non-volatile memories, will be introduced.