IEEE Journal of Solid-State Circuits

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A 0.29 pJ/b 5.27 Tb/s/mm UCIe Advanced Package Link With 2.5-D CoWoS Interposer and a 0.52 pJ/b 0.448 Tb/s/mm UCIe Standard Package Link With Organic Substrate in 3 nm FinFET

A 0.29 pJ/b 5.27 Tb/s/mm UCIe Advanced Package Link With 2.5-D CoWoS Interposer and a 0.52 pJ/b 0.448 Tb/s/mm UCIe Standard Package Link With Organic Substrate in 3 nm FinFET 150 150
Author(s): Didem Turker Melek, James Vandersand, R. Navin Kumar, Pyare M. Sarkar, Prakash BS, Adrian Leuciuc, Kevin Geary, Shaojun Ma, Chirag M. Mehta, Basant Bothra, Shashi Jain, Pawan Sabharwal, Ranjan Vaish, Kirti Bhanushali, Yutong Ding, Craig Frost, John Annunziata, Krishanu Sadhu, Dimitris Kyritsis, Jeff Bostak, Ming Li, Steve Williams, Ken Chang

Abstract:

This work presents two die-to-die (D2D) wireline transceivers, one compliant with the UCIe advanced package (UCIe-AP) and the other with the UCIe standard package (UCIe-SP) standard, developed in 3 nm FinFET. The Universal Chiplet interconnect express (UCIe)-AP link has 64 RX and 64 TX data lanes in one PHY module and …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3651425
Publisher: IEEE

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HUTAO: A Reconfigurable Homomorphic Processing UniT With Cache-Aware Operation Scheduling

HUTAO: A Reconfigurable Homomorphic Processing UniT With Cache-Aware Operation Scheduling 150 150
Author(s): Sijia Lu, Wenping Zhu, Bohan Yang, Jiajun Yang, Tongwei Dai, Chen Chen, Xiangdong Han, Jinjiang Yang, Hanning Wang, Min Zhu, Shaojun Wei, Aoyang Zhang, Leibo Liu

Abstract:

Fully homomorphic encryption (FHE) enables privacy-preserving machine learning (PPML) at the cost of intensive computational overhead, which necessitates the use of domain-specific accelerators. To achieve comprehensive support for leveled FHE, this article presents a reconfigurable multi-scheme FHE processor that supports both client-side encryption/decryption and server-side evaluation. First, a reconfigurable …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3657525
Publisher: IEEE

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A 256-Point FFT Using Analog Floating-Point Computation With Post-Silicon Tuning

A 256-Point FFT Using Analog Floating-Point Computation With Post-Silicon Tuning 150 150
Author(s): Jeongtaek Chang, Jungho Lee, Yi Shen, Sangbu Yun, Qirui Zhang, Dennis Sylvester, Hun-Seok Kim, David Blaauw

Abstract:

This article presents a 256-point fast Fourier transform (FFT) processor based on an analog floating-point computation framework. A novel floating-point analog multiply-and-accumulate (FP-AMAC) unit encodes mantissas as pulse widths with a 4-bit digital exponent and operates through integrate, pulse, and reset stages with accuracy enhancements, including node pre-charge and comparator …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3659006
Publisher: IEEE

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A 40-nm Programmable Heterogeneous SoC With 5.625/0.85 MB RRAM/SRAM for Accelerating Neuro-Symbolic AI Models

A 40-nm Programmable Heterogeneous SoC With 5.625/0.85 MB RRAM/SRAM for Accelerating Neuro-Symbolic AI Models 150 150
Author(s): Che-Kai Liu, Zishen Wan, Young-Seok Noh, Mohamed Ibrahim, Samuel D. Spetalnick, Tushar Krishna, Win-San Khwa, Ashwin Sanjay Lele, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury

Abstract:

Neuro-symbolic (NeSy) artificial intelligence (AI) integrates neural learning with symbolic reasoning to enable data-efficient, interpretable, and generalizable intelligence, making it a promising paradigm for human-like cognition. However, the heterogeneous and dynamic execution patterns of NeSy models pose fundamental challenges to conventional AI hardware, which is typically optimized for dense matrix …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3658288
Publisher: IEEE

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A 77-fJ/bit 8-Gbps Adaptive-Voltage-Compatible Self-Timed Die-to-Die Link for 2.5-D and 3-D Interconnect in 3 nm

A 77-fJ/bit 8-Gbps Adaptive-Voltage-Compatible Self-Timed Die-to-Die Link for 2.5-D and 3-D Interconnect in 3 nm 150 150
Author(s): Brian Zimmer, Stephen G. Tell, C. Thomas Gray

Abstract:

This work presents a self-timed die-to-die link that serializes four data bits per pin for 2.5-D, or 3-D interconnects using a standard adaptive digital clock and voltage supply. The link achieves 8 Gbps of per-pin bandwidth with a latency of one cycle, energy efficiency of 77 fJ/b, and bandwidth density of 44…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 10
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3658215
Publisher: IEEE

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A Low-Reference-Spur Injection-Locked Clock Multiplier Using Sub-Sampling Frequency Tracking Loop and Injection Pulse Timing Calibrator

A Low-Reference-Spur Injection-Locked Clock Multiplier Using Sub-Sampling Frequency Tracking Loop and Injection Pulse Timing Calibrator 150 150
Author(s): Hyeonjun Nam, Hyogyoung An, Changmin An, Sungjin Kim, Heein Yoon

Abstract:

This article presents an injection-locked clock multiplier (ILCM) achieving the low-reference spur (spur ${}_{\mathrm {REF}}$ ) with minimal overhead of a calibrator. To remove the dominant sources of frequency error, which are frequency drift ( $f_{\mathrm {DF}}$ ), phase offset ( $\varPhi _{\mathrm {OS}}$ ), and injection-induced phase error ( $\varPhi _{\mathrm {INJ}}$ ), the ILCM …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3650135
Publisher: IEEE

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A Modular Ring-Oscillator Array Chip for Accurate Stress Testing of CMOS Aging Mechanisms

A Modular Ring-Oscillator Array Chip for Accurate Stress Testing of CMOS Aging Mechanisms 150 150
Author(s): Javier Diaz-Fortuny, Erik Bury, Robin Degraeve, Ben Kaczer

Abstract:

Ring-oscillator (RO) circuits have historically been used to characterize the performance of CMOS technologies, as they can easily expose both process variability and aging through a straightforward circuit structure. ROs are widely employed to study degradation mechanisms such as bias temperature instability (BTI) and hot carrier degradation (HCD), which progressively …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3653472
Publisher: IEEE

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A 4.21-to-15.18 GHz Magnetically Reconfigurable and Fully Symmetrical Quad-Core Quad-Mode VCO

A 4.21-to-15.18 GHz Magnetically Reconfigurable and Fully Symmetrical Quad-Core Quad-Mode VCO 150 150
Author(s): Shijin Huang, Pei Qin, Xiang Yi, Haoshen Zhu, Liang Wu, Quan Xue

Abstract:

This work proposes a wideband low phase noise (PN) quad-core quad-mode voltage-controlled oscillator (VCO) which features magnetically reconfigurable (MR) technique and fully symmetrical architecture. The MR technique, realized through a transformer-based tank integrating an embedded switched inductor, leverages varying core excitation currents to achieve four distinct equivalent inductances, thereby enabling …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3657757
Publisher: IEEE

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Cryogenic CMOS Microwave Signal Selector Using Dual-Stage Injection-Locked Oscillator for Frequency-Multiplexed Qubit Control System

Cryogenic CMOS Microwave Signal Selector Using Dual-Stage Injection-Locked Oscillator for Frequency-Multiplexed Qubit Control System 150 150
Author(s): Hiroshi Fuketa, Ippei Akita, Hanpei Koike, Takahiro Mori

Abstract:

Cryogenic CMOS (cryo-CMOS) quantum bit (qubit) control circuits are expected to overcome the interconnect complexity problem in large-scale quantum computers. However, since each qubit has a unique frequency for control, many power-hungry oscillators are needed to generate the frequencies at the cryogenic temperature stage of a refrigerator. In this article, …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3658602
Publisher: IEEE

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