IEEE Journal of Solid-State Circuits

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A 350-pW Implantable Ventricular Arrhythmia Detection Engine With Bayesian Uncertainty Quantification in 65-nm CMOS

A 350-pW Implantable Ventricular Arrhythmia Detection Engine With Bayesian Uncertainty Quantification in 65-nm CMOS 150 150
Author(s): Zephan M. Enciso, Jianbo Liu, Boyang Cheng, Likai Pei, Steven Davis, Yifan Qin, Zhenge Jia, Xiaobo Sharon Hu, Yiyu Shi, Michael Niemier, Ningyuan Cao

Abstract:

Ventricular arrhythmias (VAs), particularly ventricular tachycardia and fibrillation, remain a leading cause of sudden cardiac death. Implantable cardioverter defibrillators (ICDs) can deliver life-saving shocks, but inappropriate shocks degrade patient outcomes and device efficiency. While deep learning has improved VA detection accuracy, it lacks uncertainty quantification (UQ), limiting clinical acceptability. This …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3669040
Publisher: IEEE

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A 10–72 GHz SDR Receiver With Compact and Low-Phase-Noise LO Frequency Quintupler

A 10–72 GHz SDR Receiver With Compact and Low-Phase-Noise LO Frequency Quintupler 150 150
Author(s): Haoyu Bai, Ling Hao, Jiazheng Zhou, Han Huang, Dong Wang, Jiaqi He, Yifei Wang, Yipeng Wang, Junhua Liu, Huailin Liao

Abstract:

This article presents a wideband receiver (RX) operating in 10–72 GHz with multiprotocol coverage, which integrates the inductor-less local oscillator (LO) frequency quintupler for down-mixing. In the LO generator, phase interpolators (PIs) are implemented to obtain five-phase pulses. Then compact edge-combining switched-capacitor (SC) based frequency quintuple techniques are proposed to output …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3669994
Publisher: IEEE

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Adelia: A 4-nm LLM Processing Unit With Streamlined Dataflow and Dual-Mode Parallelism for Maximizing Hardware Efficiency

Adelia: A 4-nm LLM Processing Unit With Streamlined Dataflow and Dual-Mode Parallelism for Maximizing Hardware Efficiency 150 150
Author(s): Sukbin Lim, Jung-Hoon Kim, Seungjae Moon, Junseo Cha, Dongjin Seo, Jongho Kim, Hunjong Lee, Jinwon Lee, Joo-Young Kim

Abstract:

The proliferation of large language models (LLMs) as cross-domain foundation models is fueled by aggressive scaling in both parameter counts and inference-time computation. The emergence of sophisticated reasoning models further accelerates this trend, demanding longer context windows and escalating the computational and memory burdens of inference. A fundamental challenge arises …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1513 – 1525
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3663603
Publisher: IEEE

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A Low Jitter and Low Spur Fractional-N Digital PLL Based on a DTC Chopping Technique

A Low Jitter and Low Spur Fractional-N Digital PLL Based on a DTC Chopping Technique 150 150
Author(s): Riccardo Moleri, Simone M. Dartizio, Michele Rossoni, Giacomo Castoro, Francesco Tesolin, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino

Abstract:

This work presents a digital-to-time converter (DTC)-based fractional-N digital phase-locked loop (PLL) designed to achieve simultaneously low jitter and low spurs. We introduce a novel DTC chopping technique that effectively mitigates fractional spurs, which we identify as predominantly arising from even-order nonlinearity invariable-slope (VS) DTCs. The proposed technique suppresses …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 17
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3663074
Publisher: IEEE

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A K/Ka-Band Transmit/Receive Front-End With Triple-Coupled Transformer Technique in 65-nm Bulk CMOS

A K/Ka-Band Transmit/Receive Front-End With Triple-Coupled Transformer Technique in 65-nm Bulk CMOS 150 150
Author(s): Nayu Li, Ziyao Xiong, Botao Yang, Hang Lu, Yiwei Liu, Xiaokang Qi, Gaopeng Chen, Na Yan, Chunyi Song, Zhiwei Xu

Abstract:

This article presents a K/Ka-band transmit/receive (T/R) front-end for jointed sensing and communication (JSAC) applications. A reconfigurable matching network for both signal reception and transmission is realized using the proposed triple-coupled transformer (TCT) technique, achieving low power loss and a compact footprint. The T/R switch at …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3667736
Publisher: IEEE

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A 142–164-GHz Phased-Array AiP Module With High-Power-Density and High-Efficiency Transceiver in 65-nm CMOS for 6G UE

A 142–164-GHz Phased-Array AiP Module With High-Power-Density and High-Efficiency Transceiver in 65-nm CMOS for 6G UE 150 150
Author(s): Yudai Yamazaki, Yohei Morishita, Sunghwan Park, Takaya Uchino, Chenxin Liu, Jun Sakamaki, Akihiro Egami, Ryosuke Hasaba, Ken Takahashi, Tomoki Abe, Tomohiro Murata, Yoichi Nakagawa, Takashi Tomura, Hiroshi Taneda, Kei Murayama, Makoto Tsukahara, Hiroko Ota, Yoko Nakabayashi, Ryuji Kinugawa, Takumi Kojima, Anyi Tian, Kotaro Ito, Chun Wang, Hans Herdian, Yi Zhang, Zheng Li, Wenqian Wang, Hongye Huang, Dingxin Xu, Sena Kato, Michihiro Ide, Shinsuke Hara, Issei Watanabe, Akifumi Kasamatsu, Yuncheng Zhang, Hiroyuki Sakai, Kazuaki Kunihiro, Atsushi Shirane, Koji Takinami, Kenichi Okada

Abstract:

This work presents a D-band high-power-density four-element phased-array transceiver for 6G user equipment (UE). Conventional designs require large multi-stage LO generation circuits for D-band up/down conversion, making it difficult to achieve compact size and low-power consumption. To address this, we propose an integrated LO chain using an injection-locked tripling …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1275 – 1293
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3665184
Publisher: IEEE

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A 28-nm Hybrid-Domain Outer Product-Based Floating-Point SRAM Computing-in-Memory Macro With Logarithm Bit-Width Residual ADC for Edge AI

A 28-nm Hybrid-Domain Outer Product-Based Floating-Point SRAM Computing-in-Memory Macro With Logarithm Bit-Width Residual ADC for Edge AI 150 150
Author(s): Yiyang Yuan, Zhongyi Sun, Yiming Yang, Xinghua Wang, Xiaoran Li, Cailian Ma, Qirui Chen, Meini Tang, Xi Wei, Hao Wu, Haitao Wang, Qihao Liu, Chengying Chen, Jinshan Yue, Pui-In Mak, Feng Zhang

Abstract:

With increasingly sophisticated artificial intelligence (AI) applications, there is an escalating need for computing-in-memory (CIM) schemes to facilitate high-precision floating-point (FP) multiply accumulate (MAC) computing, while existing digital or analog CIM implementations exhibit inherent limitations when confronted with high-bit precision situations. Therefore, this work presents a hybrid-domain CIM macro to …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3668132
Publisher: IEEE

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A 1.16 e-rms Temporal Random Noise, 123-dB High Dynamic Range, 2.988-μm Pitch 3-Mpixel Three-Stacked Digital Pixel Sensor for Versatile Applications

A 1.16 e-rms Temporal Random Noise, 123-dB High Dynamic Range, 2.988-μm Pitch 3-Mpixel Three-Stacked Digital Pixel Sensor for Versatile Applications 150 150
Author(s): Min-Woong Seo, Yong-Suk Choi, Sanggwon Lee, Yeongseok Shim, Gihwan Cho, Daehee Bae, Masamichi Ito, Jaehun Jeong, Hiroyuki Sugihara, Si-Gyoung Koo, Sung-Jae Byun, Hyukbin Kwon, Youna Lee, Bumjun Kim, Su-Hyun Han, Suksan Kim, Wonoh Ryu, Kwan-Sik Kim, Yongjun Kim, Seung-Sik Kim, Junghoon Jung, Sun-Young Yoo, Jinkyeong Heo, Seung-Chul Shin, Heesung Shim, Jae-Kyu Lee, Jonghyun Go, Jaihyuk Song

Abstract:

This article presents a 3-Mpixel (Mp) three-stacked digital pixel sensor (DPS) featuring the world’s smallest pixel pitch of $2.988~\mu $ m, achieving a low temporal random noise (RN) of 1.16 e-rms and a high dynamic range (HDR) of 123 dB in global-shutter (GS) operation mode for versatile applications. To realize both the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1319 – 1332
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3663214
Publisher: IEEE

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A Dual-Band Simultaneous RF Energy Harvesting System With Globally Optimized 3-D MPPT and Efficiency Enhancement

A Dual-Band Simultaneous RF Energy Harvesting System With Globally Optimized 3-D MPPT and Efficiency Enhancement 150 150
Author(s): Xiaguang Li, Qing Miao, Shiheng Yang, Tianting Zhao, Sijun Du, Xiaoyang Zeng, Zhiyuan Chen

Abstract:

This article presents a globally optimized radio frequency (RF) energy harvesting system that leverages the novel concepts of 3-D maximum power point tracking (3-D MPPT) and collaborative source reconfiguration to achieve high MPPT accuracy and a wide input power range. The proposed 3-D MPPT coordinates the energy sources, optimizes the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3662153
Publisher: IEEE

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