IEEE Journal of Solid-State Circuits

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Gain-Boosted N-Path Receiver With Harmonic Suppression and Scalable Clock Bootstrapping

Gain-Boosted N-Path Receiver With Harmonic Suppression and Scalable Clock Bootstrapping 150 150
Author(s): Soroush Araei, Mohammad Barzgari, Haibo Yang, Negar Reiskarimian

Abstract:

This work presents a gain-boosted N-path receiver resilient to harmonic blockers by embedding harmonic-reset switching in the feedback path. A three-stage pipeline mixer is used for downconversion, enhancing conversion gain and extending third- and fifth-order harmonic rejection (HR). To reduce power consumption and ensure reliable operation at a 0.6-V supply, …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3676868
Publisher: IEEE

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A 71–86-GHz 1024-QAM Direct-Carrier Phase-Modulating Transmitter With Digital-to-Phase Converter and Constant-Envelope Phasor Combiner

A 71–86-GHz 1024-QAM Direct-Carrier Phase-Modulating Transmitter With Digital-to-Phase Converter and Constant-Envelope Phasor Combiner 150 150
Author(s): Jia Zhou, Jieqiong Du, Chao-Jen Tien, Christopher Chen, Jhih-Wei Chen, Lachlan Cuskelly, Francisco Cardenas Beltran, Adrian Tang, Sai-Wang Tam, Mau-Chung Frank Chang

Abstract:

This article presents a 71–86-GHz 1024-QAM direct-carrier phase-modulating transmitter (DCPM-TX) that synthesizes high-order QAM symbols using phase modulation only. The proposed approach employs dual 9-bit digital-to-phase converters (DTPCs) and a constant-envelope phasor combiner. Each DTPC uses coarse/fine-segmented digitally controlled switched-capacitor transmission lines (SCTLs) (true-time-delay operation) plus a sign mixer, …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3668153
Publisher: IEEE

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A 12-bit 1-GS/s Single-Channel Pipelined ADC With Open-Loop Floating Inverter Amplifier and Residue-Dependent Integration Time Compensation

A 12-bit 1-GS/s Single-Channel Pipelined ADC With Open-Loop Floating Inverter Amplifier and Residue-Dependent Integration Time Compensation 150 150
Author(s): Hongjiang Chen, Yuhang Peng, Liang Qi, Biao Wang, Sai-Weng Sin, Rui P. Martins, Mingqiang Guo

Abstract:

A 12-bit 1-GS/s three-stage pipelined analog-to-digital converter (ADC) employing an analog compensation technique to enhance residue amplifier (RA) gain linearity is presented. The proposed residue-dependent integration time compensation (RITC) technique mitigates the compressing nonlinearity in an RA by scaling the integration time for large RA input signals. This technique …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3671779
Publisher: IEEE

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New Associate Editor

New Associate Editor 150 150
Author(s): Boris Murmann

Abstract:

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Published in: IEEE Journal of Solid-State Circuits
Page(s): 1271 – 1271
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3667077
Publisher: IEEE

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Guest Editorial Introduction to the Special Section on the 2025 Symposium on VLSI Circuits

Guest Editorial Introduction to the Special Section on the 2025 Symposium on VLSI Circuits 150 150
Author(s): Sugako Otani, John Wuu

Abstract:

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Published in: IEEE Journal of Solid-State Circuits
Page(s): 1272 – 1274
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3669685
Publisher: IEEE

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A 16 MHz RC Frequency Reference With ±450 ppm Inaccuracy From –45 °C to 85 °C After Accelerated Aging

A 16 MHz RC Frequency Reference With ±450 ppm Inaccuracy From –45 °C to 85 °C After Accelerated Aging 150 150
Author(s): Karimeldeen Mohamed, Nandor G. Toth, Hui Jiang, Çağrı Gürleyük, Kofi A. A. Makinwa

Abstract:

This article presents a high-accuracy, low-drift 16MHz RC frequency reference implemented in a standard 180 nm CMOS process. It consists of a frequency-locked loop (FLL), which locks the output frequency of a digitally controlled oscillator (DCO) to the time constant of a Wien Bridge (WB) filter. A PNP-based temperature sensor (TS) …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 9
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3673972
Publisher: IEEE

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A Noise-Shaping SAR-Based ExG Sensing Frontend With Dynamic Input-Impedance Boosting and Prediction-Assisted Mismatch-Shaping DEM

A Noise-Shaping SAR-Based ExG Sensing Frontend With Dynamic Input-Impedance Boosting and Prediction-Assisted Mismatch-Shaping DEM 150 150
Author(s): Yiming Han, Linran Zhao, Yaoyao Jia

Abstract:

This article presents a noise-shaping successive approximation register (NS-SAR)-based direct-digitizing electrophysiological (ExG) sensing frontend (SFE) fabricated in a standard 180-nm CMOS process. To address the challenges of large motion artifacts and high electrode–tissue impedance (ETI), we propose three key innovations in our proposed SFE that enable accurate ExG …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3674986
Publisher: IEEE

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A Hybrid Touch Sensing AFE With Common-CVQ (Currents, Voltages, and Charges) Subtraction to Improve Display Noise Immunity for Large Sensing Load

A Hybrid Touch Sensing AFE With Common-CVQ (Currents, Voltages, and Charges) Subtraction to Improve Display Noise Immunity for Large Sensing Load 150 150
Author(s): Seung Hun Choi, Jun Yeol An, Jaewoong Ahn, Si-Woo Kim, Jae-Youl Lee, Yoon-Kyung Choi, Hyung-Min Lee

Abstract:

On-cell touch flexible organic light-emitting diode (OLED) displays face significant display noise (D-noise) challenges due to large parasitic capacitance ( $C_{P}$ ). To address the limitations of conventional methods, this article proposes improved common-current subtraction (CCS), incorporating common-voltage subtraction (CVS) and common-charge subtraction (CQS) techniques. CVS enhances signal-to-noise ratio (SNR) by …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3675678
Publisher: IEEE

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An Array-Based IC for the Characterization of Aging in Standard Cells

An Array-Based IC for the Characterization of Aging in Standard Cells 150 150
Author(s): Andrés Santana-Andreo, José Manuel Gata-Romero, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández

Abstract:

As aging effects become more pronounced in scaled technologies, designing aging-tolerant circuits with minimal guardband overhead is increasingly critical. This requires accurate propagation of transistor-level degradation to the circuit level. In multi-input standard cells, each internal timing path can exhibit varying susceptibility to aging, a challenge compounded by the inherently …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3669600
Publisher: IEEE

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