IEEE Journal of Solid-State Circuits

A 28-nm Digital Transpose SRAM Compute-in-Memory Macro With Accurate/Approximate Dual Mode for Floating-Point Edge Training and Inference

A 28-nm Digital Transpose SRAM Compute-in-Memory Macro With Accurate/Approximate Dual Mode for Floating-Point Edge Training and Inference 150 150

Abstract:

Static random-access memory (SRAM)-based computing-in-memory (CIM) macros have been widely studied to improve the energy efficiency of edge artificial intelligence (AI) inference tasks. However, less attention has been given to AI training, which requires CIM macros to not only perform matrix multiply-accumulate (MAC) operations but also support matrix transposition. …

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A Wide-Dynamic-Range Photovoltaic Energy Harvester With Adaptive Power-Scalable MPPT Control and Direct Power-to-Digital Converter

A Wide-Dynamic-Range Photovoltaic Energy Harvester With Adaptive Power-Scalable MPPT Control and Direct Power-to-Digital Converter 150 150

Abstract:

This article presents a photovoltaic energy harvester (PVEH) that achieves high maximum power point tracking (MPPT) efficiency and power conversion efficiency across a $100~000{\times }$ input power dynamic range (DR) (from $10~{\mu }$ W to 1W). Wide-dynamic-range operation is challenging due to the inherent tradeoff between MPPT accuracy and controller power consumption. …

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An 8-bit 4.8-GS/s Four-Channel Time-Interleaved SAR ADC With Ping-Pong Comparators Using Global-Dither-Based Timing-Skew Calibration and Bit-Distribution-Based Offset Calibration

An 8-bit 4.8-GS/s Four-Channel Time-Interleaved SAR ADC With Ping-Pong Comparators Using Global-Dither-Based Timing-Skew Calibration and Bit-Distribution-Based Offset Calibration 150 150

Abstract:

This article presents a global-dither-based timing-skew calibration technique for time-interleaved (TI) analog-to-digital converters (ADCs). By injecting a dithered reference signal globally at the input buffer, the proposed method ensures negligible residual timing skews after calibration. A dither-injection scheme based on source-follower (SF) addition is proposed to suppress the dither kickback …

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A 60-V High-Side / In-Line Instrumentation Amplifier With 54-V/μs CM Transient Tolerance and 115-dB Dynamic Range

A 60-V High-Side / In-Line Instrumentation Amplifier With 54-V/μs CM Transient Tolerance and 115-dB Dynamic Range 150 150

Abstract:

A high-voltage instrumentation amplifier (HV-IA) is proposed for high-side/in-line current sensing. To achieve low noise and high common-mode (CM) transient tolerance, the IA uses an HV transient-tailored (HV-TT) PMOS input pair with a bidirectional transient shifter (BTS) in the input chopper, achieving 54-V/ $\mu $ s CM transient tolerance (17–37-V …

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A 6.5-pJ/Step Reconfigurable Readout IC With Duty-Cycled Resistor and Switched Capacitor for High Linearity RC-to-Digital Converter

A 6.5-pJ/Step Reconfigurable Readout IC With Duty-Cycled Resistor and Switched Capacitor for High Linearity RC-to-Digital Converter 150 150

Abstract:

The time-domain, reconfigurable resistance (R) and capacitance (C)-to-digital converter (RCDC) combines a Wheatstone bridge (WhB), a duty-cycled resistor (DCR), and a switched capacitor to realize a pulsewidth-locked loop (PWLL) and a frequency-locked loop (FLL) for highly linear and energy-efficient R&C sensor readout. A low-frequency, relaxation voltage-controlled oscillator (VCO) …

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A 76-Gb/s DSP-DAC-Based Discrete Multitone Wireline Transmitter in 5-nm FinFET

A 76-Gb/s DSP-DAC-Based Discrete Multitone Wireline Transmitter in 5-nm FinFET 150 150

Abstract:

This article presents a 76-Gb/s digital-to-analog converter (DAC)-based discrete multitone (DMT) wireline transmitter (TX) fabricated in 5-nm FinFET. The TX employs a 16-way parallel multi-path delay feedback (MDF) inverse fast Fourier transform (IFFT) processor for area-efficient implementation. The TX digital signal processor (DSP) includes on-chip bit/power-loading and …

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A Compact Energy-Efficient Unified Micro-Robotic Processor With Flexible Visual Perception

A Compact Energy-Efficient Unified Micro-Robotic Processor With Flexible Visual Perception 150 150

Abstract:

This work presents a programmable processor for both neural-network (NN)-based inference and localization in micro-robotic visual perception (VP). While specialized accelerators for the two applications demonstrate substantial energy efficiency and throughput gains, the built-in system with separate cores suffers from a mismatch across diverse robotic tasks, making it difficult …

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Cygnus: A Heterogeneous Octa-Core RISC-V Vector Processor for Digital Signal Processing Applications

Cygnus: A Heterogeneous Octa-Core RISC-V Vector Processor for Digital Signal Processing Applications 150 150

Abstract:

We introduce Cygnus, an energy-efficient octa-core RISC-V vector processor, compliant with the RISC-V vector extension (RVV) 1.0 specification, specifically designed for digital signal processing (DSP) and robotics applications. This system-on-chip (SoC) features dynamic instruction scheduling with short-vector lengths at the vector core level and employs a big/little architecture with tightly …

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A LEGO-Like Easy-Stacking SC Boost Converter

A LEGO-Like Easy-Stacking SC Boost Converter 150 150

Abstract:

This work presents an ultra-lightweight and small total PCB volume LEGO-like easy-stacking switched-capacitor (ESSC) step-up DC–DC converter with all input-voltage-stress-only devices for micro-actuator drivers. The proposed converter can achieve a very high-voltage conversion ratio (VCR) by multi-basic-cell stacking (BCS) with stacked power stages, level shifters (LSs), and drivers. The …

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