IEEE Journal of Solid-State Circuits – Journals

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Guest Editorial Introduction to the Special Section on the 2025 IEEE International Solid-State Circuits Conference (ISSCC)

Guest Editorial Introduction to the Special Section on the 2025 IEEE International Solid-State Circuits Conference (ISSCC) 150 150
Author(s): Hyo Gyuem Rhew, Heein Yoon, Chia-Hsiang Yang, Utsav Banerjee, Xueqing Li

Abstract:

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Published in: IEEE Journal of Solid-State Circuits
Page(s): 4 – 7
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3636764
Publisher: IEEE

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New Associate Editor

New Associate Editor 150 150
Author(s): Boris Murmann

Abstract:

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Published in: IEEE Journal of Solid-State Circuits
Page(s): 3 – 3
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3638268
Publisher: IEEE

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A 1.54-pJ/b 64-Gb/s 16-QAM Intradyne Coherent Optical Receiver in 28-nm CMOS

A 1.54-pJ/b 64-Gb/s 16-QAM Intradyne Coherent Optical Receiver in 28-nm CMOS 150 150
Author(s): Ahmed E. Abdelrahman, Mohamed Badr Younis, Mohamed Osama Selim, Mohamed Saad Aly, Mahmoud A. Khalil, Pavan Kumar Hanumolu

Abstract:

The rapid growth of data-intensive applications in modern data centers is driving demand for scalable, high-speed, and energy-efficient optical interconnects. Traditional noncoherent modulation schemes, such as pulse amplitude modulation (PAM), are reaching their scalability limits at higher data rates, making coherent detection increasingly attractive due to its higher spectral efficiency. …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 20 – 32
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3635729
Publisher: IEEE

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SHINSAI: A 586 mm2 Reusable Active TSV Interposer With Programmable Interconnect Fabric and 512 Mb Underdeck Memory

SHINSAI: A 586 mm2 Reusable Active TSV Interposer With Programmable Interconnect Fabric and 512 Mb Underdeck Memory 150 150
Author(s): Haozhe Zhu, Bo Jiao, Yuman Zeng, Yongjiang Li, Jie Liao, Siyao Jia, Zexing Chen, Liyu Lin, Xuanda Lin, Suchang Huang, Mochen Tian, Jundong Zhu, Dexin Wen, Yan Wang, Yu Wang, Jian Xu, Feng Wang, Jun Tao, Chixiao Chen, Qi Liu, Ming Liu

Abstract:

This article presents SHINSAI—a 586 mm2 reusable active through-silicon via (TSV) interposer addressing key challenges in multi-chiplet integration (MCI) architectures. While active interposers overcome fundamental limitations of passive counterparts by integrating functional circuitry, existing solutions face three critical constraints: 1) non-recurring engineering (NRE) costs from application-specific interposers negating chiplet reuse benefits; 2) …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 90 – 102
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3623630
Publisher: IEEE

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kNOT: A 2-D Distributed Network-on-Textile Architecture With Direct Die-to-Yarn Integration of 0.6 × 2.15 mm2 SoC and bySPI Chiplets for Wearable Computing

kNOT: A 2-D Distributed Network-on-Textile Architecture With Direct Die-to-Yarn Integration of 0.6 × 2.15 mm2 SoC and bySPI Chiplets for Wearable Computing 150 150
Author(s): Anjali Agrawal, Zhenghong Chen, Braden E. Desman, Jinhua Wang, Akiyoshi Tanaka, Fahim Foysal, Charles D. Hess, Will Farrell, Jim Owens, Daniel S. Truesdell, Benton H. Calhoun

Abstract:

This article presents kNOT, a scalable, distributed, and 2-D Network-On-Textile (kNOT) comprising miniaturized systems on chip (SoCs) and bypass SPI (bySPI) networking chiplets that together enable diverse networking and computational tasks. To preserve garment comfort and flexibility, kNOT eliminates bulky boards and interposers through direct-die attachment to embroidered yarns. The …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 103 – 115
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3624099
Publisher: IEEE

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A 29-Gb/mm2 1-Tb 3-b/Cell 3-D Flash Memory With CMOS Direct Bonded Array (CBA) Technology

A 29-Gb/mm2 1-Tb 3-b/Cell 3-D Flash Memory With CMOS Direct Bonded Array (CBA) Technology 150 150
Author(s): Kosuke Yanagidaira, Mario Sako, Yasuhiro Hirashima, Yumi Higashi, Yutaka Shimizu, Takeshi Nakano, Yusuke Ochi, Hiroaki Yamada, Nobushi Matsuura, Akihiro Imamoto, Kazuaki Kawaguchi, Koji Tabata, Hiroaki Hoshino, Takeshi Hioka, Shigehito Saigusa, Hiroki Date, Masaki Unno, Jumpei Sato, You Kamata, Takahiro Shimizu, Akio Sugahara, Taira Shibuya, Atsushi Okuyama, Junji Yamada, Takatoshi Minamoto, Hardwell Chibvongodze, Naoki Ojima, Hiroshi Sugawara, Masahiro Kano, Jang-Woo Lee, Hiroyuki Mizukoshi, Ryuji Yamashita, Kensaku Abe, Naohito Morozumi, In-Soo Yoon, Takuya Ariki, Jong Hak Yuh, Khin Htoo, Yosuke Kato, Yoshihiro Oyama, Yen-Lung Jason Li, Yoshihisa Watanabe, Toshiyuki Kouchi, Koji Hosono

Abstract:

This article reports a 1-Tb 3-b/cell 3-D flash memory fabricated with CMOS direct bonded array (CBA) technology. Compaction of circuits and wires achieves the highest bit density in the world over 29 Gb/mm2 with 332-word line (WL) layers. The bit density is improved by 71% from a previous generation despite …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 237 – 249
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3617579
Publisher: IEEE

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A 9-GHz Low-In-Band Noise Sub-Sampling-Chopper PLL With Charge-Share Canceling Technique

A 9-GHz Low-In-Band Noise Sub-Sampling-Chopper PLL With Charge-Share Canceling Technique 150 150
Author(s): Xiangjian Kong, Kai Xu, Huanlin Xie, Mingchao Jian, Hao Lian, Robert Bogdan Staszewski, Chunbing Guo

Abstract:

This article presents a low-jitter sub-sampling chopper phase-locked loop (SS-CPLL) that incorporates a novel chopping charge pump (C-CP) to mitigate 1/f noise in short-channel devices operating at a low supply voltage of 0.75 V. A charge-share cancellation technique is introduced to suppress ripple generated by residual charge from the previous reference …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1384 – 1396
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3532504
Publisher: IEEE

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A Ping-Pong Charge-Sharing Locking PLL With Implicit Reference Doubling and Simultaneous Frequency/Duty-Cycle Calibrations

A Ping-Pong Charge-Sharing Locking PLL With Implicit Reference Doubling and Simultaneous Frequency/Duty-Cycle Calibrations 150 150
Author(s): Sayan Kumar, Teerachot Siriburanon, Sumit Dash, Patchara Sawakewang, Shuja Andrabi, Jon Strange, Khurram Muhammad, Chih-Ming Hung, Robert Bogdan Staszewski

Abstract:

We propose a new ping-pong (PP) charge-sharing locking (CSL) phase-locked loop (PLL) architecture that enhances the strength of charge-injection into the oscillator’s LC-tank using complementary charge-sharing capacitors during both positive and negative halves of the reference clock, effectively achieving an implicit $2times $ reference frequency multiplication. The design includes a …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1368 – 1383
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3535888
Publisher: IEEE

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A 32 Gb/s 0.36 pJ/bit 3 nm Chiplet IO Using 2.5-D CoWoS Package With Real-Time and Per-Lane CDR and Bathtub Monitoring

A 32 Gb/s 0.36 pJ/bit 3 nm Chiplet IO Using 2.5-D CoWoS Package With Real-Time and Per-Lane CDR and Bathtub Monitoring 150 150
Author(s): Junhui Gu, John Ma, Azhar Ahmed Chowdhury, Jianmin Guo, Xin Zhang, Jackson Ding, Hui Wang, Ken Chang

Abstract:

This article presents a high-density, single-ended non return to zero (NRZ) chiplet I/O implemented with 3 nm CMOS technology on a 2.5-D chip-on-wafer-on-substrate (CoWoS) interposer, accommodating trace lengths up to 2 mm. The design features 216 data lanes, each operating at 32 Gb/s. For the tested 2-mm trace, the channel insertion loss …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1289 – 1298
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3545483
Publisher: IEEE

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