IEEE Journal of Solid-State Circuits – Early Access

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A 22.4–25.6-GHz Ping-Pong Sub-Sampling PLL Featuring Unified Supply Voltage Level and Balanced 2nd Harmonic Extraction

A 22.4–25.6-GHz Ping-Pong Sub-Sampling PLL Featuring Unified Supply Voltage Level and Balanced 2nd Harmonic Extraction 150 150
Author(s): Yunbo Huang, Zunsong Yang, Hongyu Ren, Rui P. Martins, Yan Lu, Nan Sun, Nan Qi, Bo Li, Yong Chen

Abstract:

This article presents a millimeter-wave (mm-wave) low-jitter and low-spur ping-pong sub-sampling PLL (PP-SS-PLL) with unified supply voltage and balanced 2nd harmonic extraction. It incorporates a PP-SS phase detector (PP-SS-PD) to mitigate the tradeoff between the in-band phase noise (PN) and loop bandwidth. We utilize an SS delay-locked loop (SS-DLL) to …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3621088
Publisher: IEEE

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A 298–334-GHz Scalable Injection-Locked Phased-Array Radiator With Second-Subharmonic-Termination-Assisted Waveform Formulation for Power Enhancement

A 298–334-GHz Scalable Injection-Locked Phased-Array Radiator With Second-Subharmonic-Termination-Assisted Waveform Formulation for Power Enhancement 150 150
Author(s): Meng Yang, Liang Wu

Abstract:

This article introduces an injection-locked $4\times 2$ phased-array radiator featuring scalability in both horizontal and vertical dimensions. The system architecture is constructed by sequentially cascading four identical phase-shifting and frequency-quadrupling (PSFQ) elements in a chain-like configuration and then cohering two such chains, thereby achieving global frequency synchronization. Particularly, phase shifting and …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3624563
Publisher: IEEE

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A Bi-Directional Dual-Path Boost–Buck Hybrid Converter for High-Voltage Power Transmission Delivery Cable in Humanoid Robots

A Bi-Directional Dual-Path Boost–Buck Hybrid Converter for High-Voltage Power Transmission Delivery Cable in Humanoid Robots 150 150
Author(s): Wenjie Yang, Zhiguo Tong, Junwei Huang, Rui P. Martins, Yan Lu

Abstract:

Humanoid robots have great potential to replace human labors for various tasks in the near future. For a centralized energy storage system in humanoid robots, its battery pack (heart) is located in the main body while the energy is mostly consumed through its legs and hands, demanding thick wires (strong …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3624037
Publisher: IEEE

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DPe-CIM: A 4T-1C Dual-Port eDRAM-Based Compute-in-Memory for Simultaneous Computing and Refresh With Adaptive Refresh and Data Conversion Reduction Scheme

DPe-CIM: A 4T-1C Dual-Port eDRAM-Based Compute-in-Memory for Simultaneous Computing and Refresh With Adaptive Refresh and Data Conversion Reduction Scheme 150 150
Author(s): Do Han Kim, Minyoung Jo, Gi Seok Kim, Dong Gyun Ha, Ung Bin Oh, Donghan Ko, Jiwoo Lee, Mingu Kang, Seong-Ook Jung

Abstract:

This article presents DPe-CIM, a 4T-1C dual-port embedded dynamic random access memory (eDRAM)-based compute-in-memory (CIM) macro with adaptive refresh and data conversion reduction. DPe-CIM proposes four key features that improve area and energy efficiency: 1) dual-port eDRAM cell (DPC) separates the multiply-and-accumulate (MAC) and refresh ports, enabling simultaneous MAC …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3623117
Publisher: IEEE

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A −117.1-dB THD Audio DAC Utilizing Single Vector Quantizer for Simultaneous Mismatch and ISI Shaping

A −117.1-dB THD Audio DAC Utilizing Single Vector Quantizer for Simultaneous Mismatch and ISI Shaping 150 150
Author(s): Yuxiang Tang, Yijie Li, Kaiwen Zhou, Qi Luo, Xining Zhang, Yongda Ma, Zhiliang Hong, Jiawei Xu

Abstract:

This article presents a high-linearity, robust-jitter tolerance digital-to-analog converter (DAC) for high-fidelity audio systems. To improve the linearity, we propose a compact digital shaper utilizing a single vector quantizer (VQ) to mitigate both DAC mismatch and inter-symbol interference (ISI) with low system complexity. Two dummy current-steering DAC (IDAC) units are …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3616622
Publisher: IEEE

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A Low-Power 28-GHz Beamforming Receiver With On-Chip LO Synthesis

A Low-Power 28-GHz Beamforming Receiver With On-Chip LO Synthesis 150 150
Author(s): Pawan K. Khanna, Yu Zhao, Mahdi Forghani, Joung Won Park, Behzad Razavi

Abstract:

This article introduces a beamforming technique that employs a novel high-impedance transmission line (T-line) architecture and several other concepts to alleviate the trade-off between loss, power consumption, and phase shift resolution. An eight-element prototype receiver (RX) fabricated in 28-nm CMOS technology draws 156 mW, achieving a minimum noise figure (NF) of 3.7 …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3615160
Publisher: IEEE

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A 0.2-V Edge-Pursuit Continuous-Time Ising Machine Using Ring-Oscillator Collapse and Delay-Enabled Positive Feedback

A 0.2-V Edge-Pursuit Continuous-Time Ising Machine Using Ring-Oscillator Collapse and Delay-Enabled Positive Feedback 150 150
Author(s): Bocheng Xu, Jiahao Song, Xiyuan Tang, Haoyang Luo, Zihan Wu, Runsheng Wang, Xiaochen Bo, Yuan Wang

Abstract:

CMOS-based continuous-time (CT) Ising machines have recently emerged as promising hardware to address combinatorial optimization problems (COPs) rapidly and efficiently. Leveraging analog spin states, CT Ising machines eliminate the clock constraint for fast solving speeds and establish superposed initial states for improved solution quality. However, prior CT Ising machines suffer …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3623731
Publisher: IEEE

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A 77-GHz Hybrid TDM-MIMO Phased-Array Radar With 186-m Detection Range and 3-cm Range Resolution

A 77-GHz Hybrid TDM-MIMO Phased-Array Radar With 186-m Detection Range and 3-cm Range Resolution 150 150
Author(s): Zitong Zhang, Yuri Lu, Wentao Xu, Yuqin Zhang, Bo Cui, Chenge Hu, Zhiluo Zhang, Sheng Sun, Yixian Li, Zihao Ren, Cong Zhang, Zhixin Yin, Kangjie Zhao, Ziyao Wang, Can Liu, Ziyan Zhao, Yunhan Qian, Chunqi Shi, Leilei Huang, Guangsheng Chen, Jinghong Chen, Runxi Zhang

Abstract:

This article presents a fully integrated 77-GHz hybrid time-division-multiplexing multiple-input–multiple-output (TDM-MIMO) phased-array radar in a 55-nm CMOS process. The system integrates eight independent transmitters ( $8~{times }~1$ TXs) and two four-channel phased-array receivers ( $2~{times }~4$ RXs), achieving a $4.76{times }$ increase in detection range compared to single-input–single-output (SISO) architecture in long-range radar (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3621305
Publisher: IEEE

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A Low-Noise Digital PLL With an Adaptive Common-Mode Resonance Tuning Technique for Voltage-Biased Oscillators

A Low-Noise Digital PLL With an Adaptive Common-Mode Resonance Tuning Technique for Voltage-Biased Oscillators 150 150
Author(s): Stefano Gallucci, Francesco Tesolin, Pietro Salvi, Daniele Lodi Rizzini, Riccardo Moleri, Francesco Buccoleri, Michele Rossoni, Giacomo Castoro, Carlo Samori, Andrea Leonardo Lacaita, Simone Mattia Dartizio, Salvatore Levantino

Abstract:

This work presents a digital phase-locked loop (PLL) incorporating an adaptive common-mode (CM) resonance tuning technique applied to a voltage-biased digitally-controlled oscillator (DCO). The method leverages the principle that the sensitivity of the oscillator frequency to a dither signal injected into the gate voltage of the cross-coupled transistors diminishes to …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3618958
Publisher: IEEE

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