IEEE Journal of Solid-State Circuits – Early Access

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A 42-Gb/s Noise-Tolerant Single-Ended Clock-Referenced PAM3 Transceiver for Chiplet Interfaces

A 42-Gb/s Noise-Tolerant Single-Ended Clock-Referenced PAM3 Transceiver for Chiplet Interfaces 150 150
Author(s): Kahyun Kim, Daehoon Na, Jeongeun Song, Hajung Park, Jin-Seok Heo, Hyunjun Park, Jihee Kim, Hanseok Kim, Hyeri Roh, Jung-Hun Park, Woo-Seok Choi

Abstract:

This article describes a single-ended (SE) clock-referenced PAM3 (CR-PAM3) transceiver that achieves an energy efficiency of 0.275 pJ/b at a high data rate of 42 Gb/s. The proposed CR-PAM3 signaling provides tolerance to supply noise and reference offset in SE chiplet or die-to-die (D2D) interfaces by using forwarded clock …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3618903
Publisher: IEEE

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A Microscaling Multi-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Device

A Microscaling Multi-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Device 150 150
Author(s): Jen-Chun Tien, Ping-Chun Wu, Win-San Khwa, Ashwin Sanjay Lele, Jian-Wei Su, Chiao-Yen Cheng, Jun-Ming Hsu, Yu-Chen Chen, Le-Jung Hsieh, Jyun-Cheng Bai, Yu-Sheng Kao, Tsung-Han Lou, Jui-Jen Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang

Abstract:

The microscaling (MX) format is an emerging data representation that quantizes high-bitwidth floating-point (FP) values into low-bitwidth FP-like values with a shared-scale (SS) exponent. When implemented with computing-in-memory (CIM), MX allows an attractive tradeoff between accuracy and hardware efficiency for specific neural network (NN) workloads. This work presents the first …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3617944
Publisher: IEEE

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A Dual-Input Bidirectional Three-Level Battery Charger Using Coarse-Fine V CF Balancing and Frequency Foldback Control for Foldable Mobile Applications

A Dual-Input Bidirectional Three-Level Battery Charger Using Coarse-Fine V CF Balancing and Frequency Foldback Control for Foldable Mobile Applications 150 150
Author(s): Woojin Hong, Hyebong Ko, Jinwoo So, Woonhyung Heo, Yonghwan Cho, Jeongdu Yoo, Ho-Sung Son, Youngwoo Chung, Dong-Joon Kim, Byeonghyeon Jin, Minkyu Kwon, Kyungmin Park, Daeyong Han, Sungkye Cho, Daewoong Cho, Jung Wook Heo, Sungwoo Lee, Sungwoo Moon, Hyoung-Seok Oh, Hwayeal Yu

Abstract:

Foldable mobile applications recently have been leading the battery charger to have a slim height with a small form-factor and high efficiency at higher input voltages to increase the power density. Another trend for mobile applications is the power sharing, which enables to supply two mobile devices simultaneously. To meet …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3618150
Publisher: IEEE

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A 40.68-MHz Dual-Output Wireless Power Transfer System for Millimeter-Scale Biomedical Implants

A 40.68-MHz Dual-Output Wireless Power Transfer System for Millimeter-Scale Biomedical Implants 150 150
Author(s): Tianqi Lu, Sijun Du

Abstract:

This article presents a single-link, dual-output wireless power transfer (WPT) system operating at 40.68 MHz for miniature, high-power biomedical implants. The elevated carrier frequency enables a millimeter-scale receiver (RX) coil while maintaining link efficiency and output power comparable to low-frequency WPT designs. End-to-end (E2E) efficiency is optimized through global power …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3617375
Publisher: IEEE

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A 112-Gb/s Discrete Multitone Wireline Receiver Datapath With Time-Interleaved Time-Based ADC in 5-nm FinFET

A 112-Gb/s Discrete Multitone Wireline Receiver Datapath With Time-Interleaved Time-Based ADC in 5-nm FinFET 150 150
Author(s): Jaewon Lee, Pier-Andrea Francese, Matthias Bräendli, Thomas Morf, Marcel Kossel, Seoyoung Jang, Yujin Choi, Donggeon Kim, Taekwang Jang, Gain Kim

Abstract:

This article presents a 112-Gb/s discrete multitone (DMT) wireline receiver (RX) datapath with a 50-GS/s, 8-bit, 64-way ( $8 \times 8$ ) time-interleaved time-based analog-to-digital converter (TI-TBADC) in a 5-nm FinFET. The TBADC converts the voltage input into a time-domain quantity using a ring oscillator (ROSC). Eight-slice TBADCs, driven from the same …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3618188
Publisher: IEEE

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A Machine Learning-Inspired PAM-4 Transceiver for Medium-Reach Wireline Links

A Machine Learning-Inspired PAM-4 Transceiver for Medium-Reach Wireline Links 150 150
Author(s): Ramin Javadi, Tejasvi Anand

Abstract:

This article presents an energy-efficient machine learning-inspired PAM-4 wireline transceiver that leverages data encoding at the transmitter (Tx) and feature extraction with classification at the receiver (Rx) to compensate for channel loss ranging from 13 to 26 dB, while maintaining the bit error rate (BER)<10-11. A new consecutive symbol-to-center (CSC) encoding …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3616072
Publisher: IEEE

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An Area and Power Efficient Source Driver IC With Multi-Line Sensing Real-Time Pixel Compensation for OLED Displays

An Area and Power Efficient Source Driver IC With Multi-Line Sensing Real-Time Pixel Compensation for OLED Displays 150 150
Author(s): Jaewoong Ahn, Seung Hun Choi, Minseong Um, Jun Yeol An, Hyung-Min Lee

Abstract:

This article proposes a source driver integrated circuit (SD-IC) with a pixel compensator designed to minimize both silicon area and power consumption for organic light-emitting diode (OLED) displays. The proposed SD-IC is capable of driving ultrahigh-definition (UHD) active-matrix OLED (AMOLED) panels with a one-horizontal-time (1-H time) of $7.2~\mu $ s while …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3614134
Publisher: IEEE

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A 28-Gb/mm2 4XX-Layer 1-Tb 3-b/Cell WF-Bonding 3D-nand Flash With 5.6-Gb/s/Pin IOs

A 28-Gb/mm2 4XX-Layer 1-Tb 3-b/Cell WF-Bonding 3D-nand Flash With 5.6-Gb/s/Pin IOs 150 150
Author(s): Sang-Soo Park, Jae-Doeg Lyu, Myungjun Kim, Jaeyun Lee, Youngsun Song, Chung-Ho Yu, Hirano Makoto, Yongseok Kwon, Jong-Hoon Park, Ho-Joon Kim, Daein Lee, Donghyun Seo, Philkyu Kang, Byungrok Go, Minseok Kim, Seoyoon Jeon, Jaehwan Ryu, Jungmin Seo, Hwan-Seok Ku, Youngmin Jo, Doo-Hyun Kim, Hyunjun Yoon, Wontae Kim, Inmo Kim, Sunghoon Kim, Jiho Cho, Moosung Kim, Jae-Woo Im, Jongmin Park, Youngdon Choi, Il-Han Park, Chiweon Yoon, Hyunsuk Kim, Jaehoon Jang, Seungjae Lee, Ki-Whan Song, Sung-Hoi Hur

Abstract:

The challenge of evolving to create a memory that is shrinking compared to the previous generation while satisfying the high performance and low power required for flash memory has been present in every generation, but the recent rapid change to artificial intelligence (AI) trends is very tough, as the level …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 9
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3613774
Publisher: IEEE

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IRIS: An Energy-Efficient Spatial Computing SoC for Real-Time Interactive Rendering and Modeling With Surface-Aware 3-D Gaussian Splatting

IRIS: An Energy-Efficient Spatial Computing SoC for Real-Time Interactive Rendering and Modeling With Surface-Aware 3-D Gaussian Splatting 150 150
Author(s): Seokchan Song, Seryeong Kim, Wonhoon Park, Jongjun Park, Sanghyuk An, Gwangtae Park, Minseo Kim, Hoi-Jun Yoo

Abstract:

The 3-D Gaussian splatting (3DGS), based on a machine learning-driven radiance field technique, is rapidly emerging as a next-generation solution in 3-D graphics. Owing to its short modeling time, computational simplicity, and high rendering quality, it is expected to replace traditional 3-D graphics on edge devices. However, its substantial memory …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3613707
Publisher: IEEE

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