IEEE Journal of Solid-State Circuits – Early Access

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Building Minimum-Power Digital Circuits With Sub-Femtowatt Dynamic Leakage-Suppression Logic Standard Cells

Building Minimum-Power Digital Circuits With Sub-Femtowatt Dynamic Leakage-Suppression Logic Standard Cells 150 150
Author(s): Daniel S. Truesdell, Jacob Breiholz, Benton H. Calhoun

Abstract:

This article investigates dynamic leakage-suppression (DLS) logic for minimum-power operation in digital circuits. The DLS logic family uses a strong intrinsic subthreshold leakage reduction technique and is an emerging approach for computing applications that prioritize low active power at or beneath the nW-level. We analytically model the key operating characteristics …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3709741
Publisher: IEEE

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A 436–472 GHz 4-Element IF Beamforming Phased-Array Receiver in 65-nm CMOS

A 436–472 GHz 4-Element IF Beamforming Phased-Array Receiver in 65-nm CMOS 150 150
Author(s): Hao Guo, Hao-Tao Hu, Zhicheng Lin, Zijun Guo, Xiaoyue Xia, Kaizhe Guo, Kam Man Shum, Pui-In Mak, Chi Hou Chan

Abstract:

This article presents a 436–472GHz four-element intermediate-frequency (IF) beamforming phased-array receiver fabricated in 65-nm CMOS, targeting scalable terahertz (THz) phased-array systems. The proposed receiver adopts a two-step mixing scheme to reduce the area overhead of the IF beamforming implementation, thereby enhancing the array scalability at THz frequencies. Each receive channel …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3710258
Publisher: IEEE

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A Three-Level Dual-Path Hybrid Buck Converter With Mitigated Capacitive Current and Seamless DVS Across a Wide Output Voltage Range

A Three-Level Dual-Path Hybrid Buck Converter With Mitigated Capacitive Current and Seamless DVS Across a Wide Output Voltage Range 150 150
Author(s): Jae-Hyun Kim, Jun-Gi Lee, Hyunki Han, Hyun-Sik Kim

Abstract:

This article presents a three-level dual-path (TLDP) buck converter tailored for mobile application processors (APs) with a 1.8-V input and 0.4–1.5-V output range. Conventional buck (CB) and multi-level buck (MLB) converters suffer from prohibitive DC resistance ( $R_{\mathrm {DCR}}$ ) losses in compact inductors as load current increases. Although various multi-path …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3710310
Publisher: IEEE

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A 0.1514-pJ/bit 18-Gb/s/wire Run-Length-Tolerant Transition-Driven AC-Coupled Transceiver for Die-to-Die Interfaces

A 0.1514-pJ/bit 18-Gb/s/wire Run-Length-Tolerant Transition-Driven AC-Coupled Transceiver for Die-to-Die Interfaces 150 150
Author(s): Jun-Cheol Lee, Joo-Hyung Chae

Abstract:

This article presents a transition-driven AC-coupled transceiver (TRX) optimized for low-power and compact die-to-die (D2D) interfaces. To address the limitations of conventional PMOS- and transimpedance-amplifier (TIA)-based receivers (RXs), the proposed RX architecture employs a small 130-fF coupling capacitor to capture only transition information, eliminating the need for bulky …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3708634
Publisher: IEEE

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A Low-Spur Fractional-N DPLL With Analog Pre-Distortion DTC Implementing Second-/Third-Order Calibration

A Low-Spur Fractional-N DPLL With Analog Pre-Distortion DTC Implementing Second-/Third-Order Calibration 150 150
Author(s): Daxu Zhang, Yuncheng Zhang, Dingxin Xu, Hongye Huang, Waleed Madany, Zezheng Liu, Wenqian Wang, Yuang Xiong, Ashbir Aviat Fadila, Duo Li, Minzhe Tang, Dongfan Xu, Atsushi Shirane, Kenichi Okada

Abstract:

This article presents a low-spur, low-jitter fractional-N digital phase-locked loop (DPLL) employing an analog pre-distortion digital-to-time converter (APD-DTC) to suppress fractional spurs by compensating for both second- and third-order nonlinearities without using complex digital pre-distortion. To support background calibration, a spur-level detection scheme using phase detector gain (PDG) is proposed …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 17
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3706350
Publisher: IEEE

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A 27-Gb/s/pin Inverter-Based Delay-Matched PAM-3 Transceiver With Pattern-Selective Switching Jitter Compensation for Die-to-Die Interfaces

A 27-Gb/s/pin Inverter-Based Delay-Matched PAM-3 Transceiver With Pattern-Selective Switching Jitter Compensation for Die-to-Die Interfaces 150 150
Author(s): Changmin Sim, Seongcheol Kim, Seungwoo Park, Junseob So, Hwaseok Shin, Taehwan Kim, Seon-Been Lee, Minkyun Shim, Chulwoo Kim

Abstract:

This article presents a 27-Gb/s/pin inverter-based delay-matched three-level pulse amplitude modulation (PAM-3) transceiver for short-reach die-to-die (D2D) interfaces. The proposed design uses two parallel, identical offset-programmable transimpedance amplifiers (TIAs) to independently generate two finely tunable PAM-3 reference levels with minimal parasitic loading, enabling multi-level signaling within a …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 17
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3706449
Publisher: IEEE

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Verifica: Near-Memory Symbolic Interval Computing Formal Neural Network Verification Accelerator

Verifica: Near-Memory Symbolic Interval Computing Formal Neural Network Verification Accelerator 150 150
Author(s): Edward Jongyoon Choi, Byeongseon Choi, Jiho Chun, Minkyu Je, Bongjin Kim

Abstract:

Formal robustness verification of neural networks is essential for deploying machine learning (ML) systems in safety-critical applications. However, existing verification frameworks are predominantly software-based, incurring prohibitive computational costs and long runtimes, severely limiting scalability and practical deployment. Although symbolic interval analysis enables scalable over-approximate verification, its effectiveness is limited by …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3707324
Publisher: IEEE

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A 0.38-pJ/step Pulse-Width Locked Time-Domain Wheatstone Bridge Sensor Readout IC for LIG-Based Wearable Strain Sensing System

A 0.38-pJ/step Pulse-Width Locked Time-Domain Wheatstone Bridge Sensor Readout IC for LIG-Based Wearable Strain Sensing System 150 150
Author(s): Siyuan Xu, Longhuang Li, Yiyang Du, Huiru Yang, Huaiyu Ye, Huan Hu

Abstract:

This article presents a pulse-width locked-loop (PWLL) time-domain readout integrated circuit (IC) for wearable strain-sensing systems based on a laser-induced graphene (LIG) strain sensor. A time-domain Wheatstone bridge (WhB) architecture is proposed, incorporating a duty-cycled resistor (DCR) and a voltage-controlled oscillator (VCO)-based integrator to realize a digitally intensive, energy-efficient, …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3704204
Publisher: IEEE

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A Nesting-Connected Reconfigurable SC Converter With Fine-Grained Conversion Ratios and Increased Output Conduction Paths for On-Chip Surround Power Delivery

A Nesting-Connected Reconfigurable SC Converter With Fine-Grained Conversion Ratios and Increased Output Conduction Paths for On-Chip Surround Power Delivery 150 150
Author(s): Xuchu Mu, Yang Jiang, Xin Ming, Bo Zhang, Rui P. Martins, Pui-In Mak

Abstract:

This article presents a reconfigurable switched-capacitor (SC) DC–DC converter that achieves improved overall efficiency over a fine-grained conversion-ratio range, applicable to on-chip surround power delivery (SPD) in compact and lightweight devices. We propose a nesting-connected reconfigurable SC topology generation method, attaining fine-grained subdivision of reconfigurable voltage conversion ratios (VCRs) …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3702012
Publisher: IEEE

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