IEEE Journal of Solid-State Circuits – Early Access

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FSL-HDnn: A 40-nm Few-Shot On-Device Learning Accelerator With Integrated Feature Extraction and Hyperdimensional Computing

FSL-HDnn: A 40-nm Few-Shot On-Device Learning Accelerator With Integrated Feature Extraction and Hyperdimensional Computing 150 150
Author(s): Weihong Xu, Chang Eun Song, Haichao Yang, Leo Liu, Meng-Fan Chang, Carlos H. Diaz, Tajana Rosing, Mingu Kang

Abstract:

This article introduces FSL-HDnn, an energy-efficient accelerator that implements the end-to-end pipeline of feature extraction (FE) and on-device few-shot learning (FSL). The accelerator addresses fundamental challenges of on-device learning (ODL) for resource-constrained edge applications through two synergistic modules: a parameter-efficient feature extractor (FE) employing weight clustering and an FSL classifier …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3709217
Publisher: IEEE

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A Performance Comparison Between W-Band Sequential and Doherty Power Amplifiers for Power Back-Off Efficiency Improvement

A Performance Comparison Between W-Band Sequential and Doherty Power Amplifiers for Power Back-Off Efficiency Improvement 150 150
Author(s): Yahia Ibrahim, Ali M. Niknejad

Abstract:

This work presents a W-band sequential power amplifier (PA) featuring a compact and low-loss output combiner that enhances power back-off (PBO) efficiency by combining a main PA and an auxiliary PA through an isolated combining output network. The proposed architecture is analyzed and experimentally compared to the conventional Doherty PA (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3708783
Publisher: IEEE

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An Extendable Wideband Band-Divided SPnT Switch Topology Based on a Reconfigurable Pole-to-Throw Network

An Extendable Wideband Band-Divided SPnT Switch Topology Based on a Reconfigurable Pole-to-Throw Network 150 150
Author(s): Zhaowu Wang, Hao Ning, Xinyan Li, Ze Yu, Qiliang Li, Xiaochen Tang, Yong Wang

Abstract:

This article presents an extendable wideband band-divided SP $n$ T switch topology based on a reconfigurable pole-to-throw network (RPTN). Compared to conventions, it mitigates the loss degradation resulting from complex signal routing in advanced RF front-ends. This is enabled by the RPTN, which divides the throws into low-/mid-/high-band (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3711644
Publisher: IEEE

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A 300-GHz 2-D Scalable 4 × 4 Phased-Array Receiver With Half-Wavelength Element Spacing in 65-nm CMOS

A 300-GHz 2-D Scalable 4 × 4 Phased-Array Receiver With Half-Wavelength Element Spacing in 65-nm CMOS 150 150
Author(s): Huanting Deng, Kaizhe Guo, Yihan Wang, Houyi Yan, Jiyao Wang, Mengru Yang, Jian Guo, Peng Gu, Xiaohu You, Dixian Zhao

Abstract:

This article presents a 300-GHz 2-D scalable $4\times 4$ phased-array receiver (RX) with half-wavelength element spacing in 65-nm CMOS. To achieve high scalability, a hybrid local oscillator (LO)–intermediate frequency (IF) beamforming scheme based on a coupled oscillator array is proposed, together with an area-efficient aperture-coupled antenna implemented on quartz. The …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3711687
Publisher: IEEE

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A Three-Level Dual-Path Hybrid Buck Converter With Mitigated Capacitive Current and Seamless DVS Across a Wide Output Voltage Range

A Three-Level Dual-Path Hybrid Buck Converter With Mitigated Capacitive Current and Seamless DVS Across a Wide Output Voltage Range 150 150
Author(s): Jae-Hyun Kim, Jun-Gi Lee, Hyunki Han, Hyun-Sik Kim

Abstract:

This article presents a three-level dual-path (TLDP) buck converter tailored for mobile application processors (APs) with a 1.8-V input and 0.4–1.5-V output range. Conventional buck (CB) and multi-level buck (MLB) converters suffer from prohibitive DC resistance ( $R_{\mathrm {DCR}}$ ) losses in compact inductors as load current increases. Although various multi-path …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3710310
Publisher: IEEE

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The Regulated Resonant Sigma Converter: A Hybrid Topology With Balanced Efficiency, Speed, and Density

The Regulated Resonant Sigma Converter: A Hybrid Topology With Balanced Efficiency, Speed, and Density 150 150
Author(s): Yukan Du, Shengdao Ren, Zheyuan Fei, Ziteng Chen, Menglian Zhao, Chushan Li, Yong Ding, Wuhua Li, Zhichao Tan, Wanyuan Qu

Abstract:

The growing power demands of AI processors are imposing enormous stresses on the power converters for ever higher efficiency, speed, and density (E-S-D), yet classic solutions face severe challenges in meeting all the three E-S-D targets at the same time. Aresonant sigma converter is proposed, combining a high-side switched-capacitor buck (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3711891
Publisher: IEEE

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A High-Efficiency Multilevel Class-G Supply Modulator Using a Configurable Capacitor Array for Wideband Power Amplifier

A High-Efficiency Multilevel Class-G Supply Modulator Using a Configurable Capacitor Array for Wideband Power Amplifier 150 150
Author(s): Mingchao Liang, Yu An, Peng Cao, Jiawei Xu, Zhiliang Hong

Abstract:

This article presents a multilevel class-G supply modulator (SM) for high-efficiency wideband radio frequency (RF) power amplifiers (PAs). As the envelope bandwidth of modern 5G new radio (NR) signals extends to 200 MHz, conventional analog envelope tracking (ET) suffers from limited bandwidth, while switched discrete SMs face challenges associated with high …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3711586
Publisher: IEEE

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Building Minimum-Power Digital Circuits With Sub-Femtowatt Dynamic Leakage-Suppression Logic Standard Cells

Building Minimum-Power Digital Circuits With Sub-Femtowatt Dynamic Leakage-Suppression Logic Standard Cells 150 150
Author(s): Daniel S. Truesdell, Jacob Breiholz, Benton H. Calhoun

Abstract:

This article investigates dynamic leakage-suppression (DLS) logic for minimum-power operation in digital circuits. The DLS logic family uses a strong intrinsic subthreshold leakage reduction technique and is an emerging approach for computing applications that prioritize low active power at or beneath the nW-level. We analytically model the key operating characteristics …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3709741
Publisher: IEEE

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A 436–472 GHz 4-Element IF Beamforming Phased-Array Receiver in 65-nm CMOS

A 436–472 GHz 4-Element IF Beamforming Phased-Array Receiver in 65-nm CMOS 150 150
Author(s): Hao Guo, Hao-Tao Hu, Zhicheng Lin, Zijun Guo, Xiaoyue Xia, Kaizhe Guo, Kam Man Shum, Pui-In Mak, Chi Hou Chan

Abstract:

This article presents a 436–472GHz four-element intermediate-frequency (IF) beamforming phased-array receiver fabricated in 65-nm CMOS, targeting scalable terahertz (THz) phased-array systems. The proposed receiver adopts a two-step mixing scheme to reduce the area overhead of the IF beamforming implementation, thereby enhancing the array scalability at THz frequencies. Each receive channel …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3710258
Publisher: IEEE

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