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Solid-State Circuits Directions (SSCD) Workshop: Non-Traditional Computing Paradigms with Emerging Technologies for Energy Efficiency Workshop

IEEE Region 1 (Northeastern USA)
Danielle Marinese –
Web site

Solid-State Circuits Directions (SSCD) Workshop: Non-Traditional Computing Paradigms with Emerging Technologies for Energy Efficiency Workshop

November 9, 9:00 AM - 11:30 AM ET

November 13, 9:00 AM - 11:30 AM ET 

Organized by: Sumeet Kumar Gupta, Azad Naeemi, and Ian Young

As the power reduction through device scaling slows, exploratory materials, devices, and circuits are being examined to open new paths for achieving energy-efficiency especially as the demand for information storage and processing grows exponentially. This new-found freedom of breaking out of ‘‘CMOS scaling’’ introduces many new opportunities to do things completely differently—use a different material, invent a new device that operates on a different physical mechanism, and explore a new circuit function for computing that capitalizes on the unique properties of the new devices. Research in this area is truly multidisciplinary as it brings together the researchers who are focused toward the exploration of a new device and interconnect, or function for a more energy-efficient integrated circuit for computing. Computation based on the emerging devices is not limited to just digital information processing but also encompasses non-Boolean computation, including analog, neuromorphic computing, and novel concepts in computer automata. This two-day virtual workshop brings together leading researchers in this field to present the latest advances and to discuss the challenges and opportunities that are ahead of us. 

Sumeet Gupta, Purdue University

Azad Naeemi, Georgia Institute of Technology

Ian Young, Intel Corporation



All times are in Eastern time (ET).


9:00 AM: The Solid-State Circuits Directions (SSCD) Committee Introduction

9:05 AM: Workshop Overview

9:10 AM: Prof. Asif Khan: Ferroelectric Memories

9:40 AM: Prof. Sharon Hu: Energy-Efficient In-Memory Search with Non-Volatile Content-Addressable Memories

10:10 AM: Dr. Devin Verreck: The Promise of 2-D Materials for Scaled Digital and Analog Applications

10:40 AM: Prof. Jaydeep Kulkarni: Ising-CIM: Advancing Ising Accelerators for Combinatorial Optimization Problems with Compute-in-Memory Design Approach 


11:10: Q&A and Panelist Discussion


Presented by: Prof. Jaydeep Kulkarni

Title: Ising-CIM: Advancing Ising Accelerators for Combinatorial Optimization Problems with Compute-in-Memory Design Approach

Abstract: Combinatorial optimization problems (COPs) find applications in real-world scientific, industrial, and societal scenarios. To expedite the COP computation, non-traditional computing formalism utilizing the Ising model is being investigated. An Ising model abstracts the spin dynamics in a ferromagnet wherein the spins are orientated to reach the minimum energy state, representing the optimum COP solution. Previous Ising designs utilized dedicated annealing processors or additional digital arithmetic circuits next to the memory bitcells. These custom circuits or processors cannot be repurposed for other non-COP applications, incurring significant area and power overhead. In this talk, I will present a reconfigurable and scalable compute-within-memory approach for Ising computation. This area-efficient approach repurposes existing embedded memory bitcell columns and peripheral circuits to perform analog domain Hamiltonian calculations on the bitlines, significantly minimizing area and power overhead.

Bio: Jaydeep Kulkarni is an Associate Professor in the Chandra Department of Electrical and Computer Engineering and a Fellow of Silicon Labs Endowed Chair at the University of Texas at Austin. His current research is focused on machine learning hardware accelerators, in-memory computing, DTCO/STCO aspects of emerging nano-devices and 3D/heterogeneous integrated circuits, hardware security, and cryogenic computing. His research has been recognized with the NSF CAREER Award, SRC Innovator Award, Intel Rising Star Faculty Award, and Micron Foundation Faculty Awards. He has served as a Distinguished Lecturer for IEEE SSCS and ED societies and served as a TPC member for the VLSI Symposium, ASSCC, CICC, DAC, ICCAD, and ISLPED.  

Group Website: Circuit Research Lab, 

Presented by: Prof. Sharon Hu

Title: Energy-Efficient In-Memory Search with Non-Volatile Content-Addressable Memories

Abstract: Data transfer between processors and memory presents significant challenge in enhancing application performance. This challenge becomes particularly pronounced for data intensive tasks that involve extensive search operations, as seen in various domains like machine learning, bioinformatics and security applications. In-memory search (IMS), where search is executed directly within the memory array, is a promising solution to alleviate this bottleneck. Content addressable memory (CAM) is a special memory that can directly support IMS. However, high energy consumption can be a roadblock for designing large-scale CAMs.

In this presentation, I will first introduce different CAM types, including exact and approximate match, ternary and multi-bit data representation, and diverse distance functions. I will then highlight how different non-volatile memory technologies (such as RRAM, FeFETs and Flash memory) can be exploited to implement energy-efficient CAM functions. I will further demonstrate the use of FeFET-based CAMs in an end-to-end solution to a few-shot learning application, highlighting the unique contributions of each design layer. These insights may serve as valuable guidelines for future research endeavors.

Bio: Sharon Hu is a professor in the department of Computer Science and Engineering at the University of Notre Dame, USA. She recently joined the U.S. NSF as a rotating Program Director in the Division of Computing and Communication Foundations. Her research interests include low-power system design, circuit and architecture design with emerging technologies, real-time embedded systems, and hardware-software co-design. She has published more than 450 papers in these areas. Some of her recognitions include the Best Paper Award from the Design Automation Conference and the International Symposium on Low Power Electronics and Design, and NSF Career award. She served as the General Chair and TPC Chair of Design Automation Conference, Real-Time Systems Symposium, etc. She is the Editor-in-Chief of ACM Transactions on Design Automation of Electronic Systems and served as Associate Editor of other ACM and IEEE journals.  Sharon Hu is a Fellow of the ACM and the IEEE. 

Presented by: Dr. Devin Verreck

Title: The promise of 2-D materials for scaled digital and analog applications

Abstract: The scaling roadmap of silicon channel MOSFETs is reaching its fundamental limits. In this talk, I will discuss the potential of 2-D materials to break through this barrier thanks to their sub-nm thickness. I will go from material to device to circuit level simulation assessment, highlighting benefits for scaled digital, analog and back-end-of-line applications. I will conclude with an evaluation of the experimental state-of-the-art and the remaining challenges.

Bio: Devin Verreck received the MSc degree in Nanoscience and Nanotechnology in 2012 and the PhD degree in Electrical Engineering in 2017 from the KU Leuven summa cum laude with congratulations of the board of examiners. He is now a principal researcher in the TCAD team at imec, where he develops models for the optimization of 2-D material FETs and 3-D NAND flash memories.

Presented by: Prof. Asif Khan
Title: Ferroelectric memories

Abstract: Over the last decade, the discovery of ferroelectricity in fluorite-structured binary oxides, namely HfO2 and its alloyed variants, led to resurgent interests into ferroelectric devices for memory applications. In this presentation I will focus on the latest developments in ferroelectric field-effect transistors (FEFETs) and their application in memory technologies, including embedded, and storage memories, as well as their potential uses as artificial intelligence, machine learning, and neuromorphic hardware. I will also discuss the scientific obstacles that must be overcome to integrate FEFETs into advanced technology nodes beyond 10nm, as well as the efforts of my research team to address these challenges. 

Bio: Asif Khan is an Associate Professor in the School of Electrical and Computer Engineering with a courtesy appointment in the School of Materials Science and Engineering at Georgia Institute of Technology. Dr. Khan’s research focuses on ferroelectric devices that address the challenges faced by the semiconductor industry due to the end of transistor miniaturization. His work led to the first experimental proof-of-concept demonstration of the ferroelectric negative capacitance, which can reduce the power dissipation in transistors. His recent work includes the exploration of the reliability of ferroelectric field-effect transistors and metrology of ferroelectric devices and materials. Dr Khan’s notable awards include the DARPA Young Faculty Award (2021), the NSF CAREER award (2021), the Intel Rising Star award (2020), the Qualcomm Innovation Fellowship (2012), TSMC Outstanding Student Research Award (2011) and University Gold Medal from Bangladesh University of Engineering and Technology (2011). 



All times are in Eastern time (ET).


9:00 AM: The Solid-State Circuits Directions (SSCD) Committee Introduction

9:05 AM: Workshop Overview

9:10 AM: Dr. Victor Moroz: In Search of Design and Technology Tweaks to Achieve a Breakthrough in Reducing Server Farm Power Consumption

9:40 AM: Dr. Punyashloka Debashis and Dr. Hai Li: Magneto-Electric Spin Orbit (MESO) Device for Energy Efficient Logic

10:10 AM: Prof. Naveen Verma: Future Prospects of In- and Near-Memory Computing

10:40 AM: Prof. Nikhil Shukla: Designing Dynamical Systems with Emerging Technologies to Solve Hard Problems


11:10: Q&A and Panelist Discussion


Presented by: Dr. Victor Moroz

Title: In search of design and technology tweaks to achieve a breakthrough in reducing server farm power consumption

Abstract: Server farms are gobbling up an increasing part of world’s electricity, and new technology generations only offer tiny improvements in power consumption. The only way to dramatically reduce power is to operate server farms at cryogenic temperatures. We explore how to tune silicon technology to optimize it for cryogenic operation and quantify the power saving benefits of operating at different cryogenic temperatures. The methodology that we use for this exploration includes optimizing key transistor properties to maximize cryogenic benefits and includes optimizing interconnects, as narrow vs wide wires have very different conductivity vs temperature trends. The transistor and interconnect behaviors are transferred into logic library behavior and finally into a logic block PPA (Power-Performance-Area) benchmarking.

Bio: Victor Moroz is a Synopsys Fellow, engaged in a variety of projects on modeling Design-Technology Co-Optimization, FinFETs, gate-all-around transistors, stress engineering, 3D ICs, transistor scaling, cryogenic devices, Middle-Of-Line and Back-End-Of-Line resistance and capacitance, solar cell design, innovative patterning, random and systematic variability, junction leakage, non-Si transistors, and atomistic effects in layer growth and doping. Several facets of this activity are reflected in three book chapters, a 100+ technical papers and over 300 US and international patents. Victor has been involved in technical committees at ITRS, IEDM, SISPAD, DFM&Y, ECS, IRPS, EDTM, and ESSDERC, including serving as a Technical Chair of SISPAD 2018 and is currently serving as an Editor of IEEE Electron Device Letters.


Presented by: Dr. Punyashloka Debashis and Dr. Hai Li

Title: Magneto-Electric Spin Orbit (MESO) device for energy efficient logic

Abstract: The development of next generation of energy efficient beyond-CMOS computing hardware will be based on low switching voltage and higher functionality logic devices. Recent advances have demonstrated the feasibility of such a logic device by utilizing magnetoelectric (ME) materials to switch a nanomagnet and using spin-orbit (SO) effects to read out its state. This talk will introduce this device, the physical principles for its operation, and present some of the key experimental advances as well as circuit modelling results. 


Material and process innovations that enabled the progression from 6V to 150 mV voltage driven switching of CoFe magnetization direction in functional magnetoelectric devices utilizing the perovskite BiFeO3 as the magnetoelectric element will be presented. Dynamic switching studies of the ferroelectric polarization upto 2ns switching will be presented. Following this, the material and device parameters affecting the readout of the magnetization state through spin-orbit effects would be discussed and the continuous improvement in the read-out signal levels in the recent years will be presented. To optimize device and its design, multiphysics simulation approach is utilized to capture the material and device behavior by a compact model within circuit simulation environments. New topologies such as MESO stacking are simulated versus pure CMOS. Novel clocking strategy is also proposed to reduce static power and latency. Besides, several primary circuit primitives are implemented with MESO device to demonstrate functionalities as logic as well as memory. 

Finally, some of the key challenges for enabling the design of high functionality beyond-CMOS logic circuits such as lowering the switching voltage to <100 mV with fast switching dynamics, improving the readout voltage >100 mV, and improving the device endurance will be summarized.


Bio: Punyashloka Debashis received B.Tech and M.Tech in Electrical Engineering from the Indian Institute of Technology Kanpur and Bombay in 2012 and 2014 respectively, and Ph.D. in Electrical and Computer Engineering from Purdue University in 2020, where he was part of the early investigation into computing using spintronics based probabilistic bits. He joined Intel Corporation in 2020 as a Research Engineer in the Components Research division in Hillsboro, Oregon. He is responsible for the integration and characterization of beyond-CMOS devices and for mentoring joint research programs with universities on nanotechnology and exploratory devices. In 2022, he won a divisional recognition award at Intel for the demonstration of magnetoelectric switching at 150 mV and another one in 2023 for developing a magnetic characterization setup for novel materials. He has 30 publications in refereed journals and conferences in spintronics and nanoelectronics, and 28 issued or submitted patents in spintronic, ferroelectric and magnetoelectric devices.

Bio: Hai Li received the B.S. degree in Applied Physics from Huazhong University of Science and Technology in 2011 and the M.S. and Ph.D. degrees in Electrical and Computer Engineering from Carnegie Mellon University in 2015 and 2016, respectively, where he developed foundational theorem of next generation storage systems.

After internships at Western Digital and Apple, he joined Intel Corporation in 2016, starting with specialized technologies program. He is currently a Senior Research Scientist in Exploratory Integrated Circuits group, Components Research, Hillsboro, OR, USA. With a focus on Multiphysics simulation, he is working on emerging technologies in the joint area of novel device, circuit, and computing paradigm, while managing university collaboration programs on nanotechnology and exploratory topics. He also serves as co-chair for Intel Emerging Technology Strategic Research Sector (SRS).


Presented by: Prof. Naveen Verma

Title: Future Prospects of In- and Near-Memory Computing

Abstract: Future data-intensive workloads, particularly from artificial intelligence, have pushed conventional computing architectures to their limits of energy efficiency and throughput, due to the scale of both computation and data they involve. In- and near-memory computing provide approaches for overcoming this, but instate fundamental tradeoffs that span the device, circuit, and architecture levels. This presentation starts by describing the methods by which in/near-memory computing derive their gains, and then examines the critical tradeoffs, looking concretely at recent designs across memory technologies (SRAM, RRAM, MRAM). Then, its focus turns to key architectural considerations, and how these are likely to drive future technological needs and application alignments. Finally, this presentation analyzes the potential for leveraging application-level relaxations (e.g., noise sensitivity) through algorithmic approaches. 

Bio: Naveen Verma received the B.A.Sc. degree in Electrical and Computer Engineering from the UBC, Vancouver, Canada in 2003, and the M.S. and Ph.D. degrees in Electrical Engineering from MIT in 2005 and 2009 respectively. Since July 2009 he has been at Princeton University, where he is currently Director of the Keller Center for Innovation in Engineering Education and Professor of Electrical and Computer Engineering. His research focuses on advanced sensing systems, exploring how systems for learning, inference, and action planning can be enhanced by algorithms that exploit new sensing and computing technologies. Prof. Verma co-founded EnCharge AI, together with industry leaders, to commercialize foundational technology for AI computation developed in his lab. Prof. Verma has served as a Distinguished Lecturer of the IEEE Solid-State Circuits Society, and on a number of conference program committees and advisory groups. Finally, he is the recipient of numerous teaching and research awards, including several best-paper awards, with his students.


Presented by: Prof. Nikhil Shukla

Title: Designing Dynamical Systems with Emerging Technologies to Solve Hard Problems

Abstract: Digital computing has enjoyed tremendous success and has become the backbone of the modern information revolution. However, the slowing down of one of its primary drivers, the Moore’s law, and the increasing application-driven necessity to compute problems that have been traditionally challenging to solve on digital machines, has created a convergent need to expand the boundaries of current computing platforms. Dynamical systems represent one such Non-von Neumann paradigm that is particularly promising for solving computationally intractable problems in combinatorial optimization.

In this presentation, I will first address the opportunities and the challenges of this computational paradigm. Against this backdrop, I will describe some of my lab’s recent experimental and theoretical results on implementing dynamical systems to solve hard combinatorial optimization problems on graphs and hypergraphs. Subsequently, I will discuss the lab’s ongoing efforts in exploring opportunities to implement such platforms efficiently using emerging hardware technologies. Finally, I will conclude by identifying some crucial performance metrics that would need to be achieved for such systems to become competitive computing platforms in the future, along with potential pathways to accomplish them.

Bio: Nikhil Shukla is currently an Assistant Professor at the University of Virginia with a joint appointment in the Department of Electrical & Computer Engineering, and the Department of Materials Science and Engineering. He also serves as the UVA deputy site director of the MIST (Multifunctional Integrated System Technology) center, an industry-university cooperative research center. Nikhil received his PhD from the University of Notre Dame in 2017. Nikhil’s research interests lie in the general area of the physics of computing, and he is presently interested in exploring opportunities for efficient computation through device-circuit-and computing model co-design. He has authored/co-authored over 70 journal and conference papers and his work on Phase transition FETs received the best paper award from IEEE TMSCS in 2017. He currently serves as a member of the IEEE Nanotechnology Council on Quantum, Neuromorphic, and Unconventional Computing, and has also served on the technical program committees of various conferences such as the Design Automation Conference (DAC).