O is a leading authority in the field of analog electronics, which he has called "a fundamental technology that touches virtually everyone's daily life." Analog technology benefits many by providing wireless communication, but it can also be used for devices focused on health or safety. It could also lead to more environmentally friendly electronic devices. O, a fellow of the Institute of Electrical and Electronics Engineers (IEEE), was recruited to direct the Texas Analog Center of Excellence (TxACE) – a project funded by the Semiconductor Research Corporation (SRC), the state through its Texas Emerging Technology Fund, Texas Instruments, the UT System and UT Dallas. TxACE opened its new 8,000-square-foot labs at UT Dallas in 2010, with O predicting great achievements from the interdisciplinary teams. "We will find solutions to some of the great challenges the world faces today through the research at this facility that brings together people from diverse backgrounds to enable technology that people working in one particular discipline couldn't come up with on their own." O received his bachelor's, master's and doctoral degrees, all in electrical engineering and computer science, from the Massachusetts Institute of Technology. Before joining UT Dallas he was a professor of electrical and computer engineering at the University of Florida in Gainesville. His mentor, MIT Provost L. Rafael Reif, was O's honored guest at his investiture ceremony at UT Dallas in November 2009. O has been married for more than 20 years and is the father of three boys.

Daniel J. Friedman (S’91—M’92) received the Ph.D. degree in engineering science from Harvard University, Cambridge, MA, in 1992. After completing consulting work at MIT Lincoln Labs and postdoctoral work at Harvard in image sensor design, he joined the IBM Thomas J. Watson Research Center, Yorktown Heights, NY, in 1994.  His initial work at IBM was the design of analog circuits and air interface protocols for field-powered RFID tags. In 1999, he joined the mixed-signal communications IC design group and turned his attention to analog circuit design for high-speed serializer/deserializer macros. He managed the mixed-signal team from 2000-2009, focusing efforts on serial data communication and clock synthesis applications. In 2009, he became senior manager of the communication circuits and systems group, adding responsibility for teams in millimeter-wave wireless and digital communications IC design. He has authored or co-authored more than 50 technical papers in circuit topics including serial links, PLLs, RFID, and imagers. He was a co-recipient of the Beatrice Winner Award for Editorial Excellence at the 2009 ISSCC and the 2009 JSSC Best Paper Award given in 2011; he holds more than 50 patents. He was a member of the ISSCC international technical program committee from ISSCC 2009 through ISSCC 2016; he served as the Wireline sub-committee chair from ISSCC 2012 through ISSCC 2016 and served as the Short Course Chair for ISSCC 2017. His current research interests include high-speed I/O design, PLL design, mmWave circuits and systems, and circuit/system approaches to enabling new computing paradigms.

ALVIN LOKE (S’90-M’99-SM’04) is an industry veteran working on CMOS technology and design since 1998, and has been an active volunteer with the IEEE Solid-State Circuits Society since 2003. He received the B.A.Sc. degree in engineering physics with highest honors from the University of British Columbia, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University. He was the recipient of a Canadian NSERC 1967 Scholarship and has interned at Sumitomo Electric Industries, Texas Instruments, and Motorola. Upon graduation, he worked several years in CMOS process integration at HP Labs and Chartered Semiconductor (as an Agilent assignee) before shifting to wireline design and design/technology interface at Agilent, Advanced Micro Devices, and Qualcomm. Alvin is presently a Director in the TSMC San Diego Design Center working on next-generation CMOS analog/mixed-signal design and technology co-optimization. He has authored over 50 publications (including a CICC 2018 Best Paper and many invited presentations) and holds 25 US patents. Alvin is currently the IEEE Solid-State Circuits Society (SSCS) Webinar Coordinator for North America, Chair of the San Diego SSCS Chapter, and VLSI Symposia committee member. In the past, he has served as a CICC 2006-2012 committee member, SSCS Fort Collins Chapter officer (2003-2013), SSCS Chapters committee member, IEEE Journal of Solid-State Circuits (JSSC) and IEEE Solid-State Circuits Letters (SSC-L) guest editor, inaugural SSCS Webinar Taskforce Chair, and SSCS Distinguished Lecturer (2012-2013). The SSCS Fort Collins chapter he led was awarded the SSCS Outstanding Chapter Award in 2005 and Denver Section Chapter of the Year three times. He also received the IEEE Region 5 Outstanding Member Service Award in 2010.

Frank O'Mahony leads the I/O Circuit Technology group within Advanced Design at Intel in Hillsboro, Oregon, where he is a Senior Principal Engineer. His team coordinates circuit-process co-design for wireline I/O at Intel. They also design and test the first I/Os on each new CMOS process technology. From 2003 until 2011 he was a member of the Signaling Research group in Intel’s Circuit Research Lab. His past work includes high-speed and low-power transceivers, clock generation and distribution, equalization, analog circuit scaling, and on-die measurement techniques. Frank received the BS, MS, and PhD degrees in electrical engineering from Stanford University. Frank has been on the ISSCC Technical Program Committee since 2012 including five years as the Wireline Subcommittee chair. He currently serves as the ISSCC Forums Chair. Since 2003 he has published over 40 papers in peer-reviewed conferences and journals on the topic of wireline transceivers and clocking. He has received the ISSCC Jack Kilby Award, IEEE Journal on Solid-State Circuits Best Paper Award and TCAS Darlington Best Paper Award. He is a Senior Member of the IEEE and served as an IEEE Distinguished Lecturer.

Woogeun Rhee received the B.S. degree from Seoul National University, Seoul, Korea, the M.S. degree from the University of California, Los Angeles, and the Ph.D. degree from the University of Illinois, Urbana-Champaign. From 1997 to 2001, he was with Conexant Systems, CA. From 2001 to 2006, he was with IBM T.J. Watson Research Center, NY. In 2006, he joined the faculty at the Institute of Microelectronics, Tsinghua University, Beijing, China and is currently a Professor. His research interests include short-range low-power transceivers and clock/frequency generation circuits for wireline and wireless communications. He holds 23 U.S. patents. Dr. Rhee was an IEEE Distinguished Lecturer of the Solid-State Circuits Society (2016-2017) and currently serves as an Associate Editor for O-JSSC. He has been an Associate Editor for JSSC (2012-2018) and a Guest Editor for JSSC Special Issue in November 2012 and November 2013. He has served as a member of several IEEE conferences, including ISSCC (2012-2016), CICC, and A-SSCC.

Ichiro Fujimori received the B.S. degree in Electrical Engineering from the Tokyo University of Science in 1985, and the PhD degree from the University of Hiroshima in 2003.

     In 1985, Dr. Fujimori joined Asahi-Kasei Microsystems (AKM), Japan. His pioneering work includes the industry first Delta-Sigma DAC for portable audio achieving 90-dB dynamic range at 1.5-V operation, and the first Delta-Sigma ADC for professional audio exceeding 123-dB dynamic range. In 2000, he joined Newport Communications (later acquired by Broadcom). As the Manager of Mixed-Signal Engineering, he led the team to the development of the first CMOS transceiver LSI’s for SONET OC-192 applications, and the first IEEE 802.3ae “10GE LAN PHY” SOC where the 10-Gbps transceivers and the sub-layer system (XAUI) were integrated on the same chip. In 2012, he was appointed Vice President of Central Engineering at Broadcom Corporation, responsible for the roadmap and development of mixed-signal IP that enables Communication SoCs for both Consumer and Network Infrastructure applications. The IP include multi-gigabit SerDes for Networking, Optical transceivers, Ethernet Copper PHYs, Automotive AFEs, PLL’s, mobile PMU, Power-Over-Ethernet and embedded Power Management circuits. He is currently the Vice President of R&D at the Mixed Signal

ASIC Product Division of Broadcom Incorporated (Avago/Broadcom merger), leading the analog ASIC development for Mobile Platforms, Satellite Communications and 5G Base-Stations.

     Dr. Fujimori is an IEEE Fellow, and the recipient the IEEE Journal of Solid-State Circuits, Best Paper Award 2000 for the paper entitled “A Multi-bit Delta-Sigma Audio DAC with 120-dB Dynamic Range.” He has published 40 technical articles including 11 ISSCC papers, and has conducted various Seminars, Invited talks, and Panels in the field of Data Converters and Wireline Communications. He has served in the Technical Program Committee of VLSI Circuits Symposium from 2009 to 2014, and in the Executive Committee since 2015. He served in the Technical Program Committee of International Solid State Circuits Conference from 2011 to 2017, and the Associate Editor of the IEEE Journal of Solid-State Circuits from 2012 to 2018. He is currently in the IEEE SSCS Fellow Evaluation Committee. He holds 35 U.S. patents.

Rikky Muller (M’04–SM’17) received the B.S. and M.S. degrees from MIT, Cambridge, MA, USA, and the Ph.D. degree from the University of California at Berkeley, Berkeley, CA, USA, all in electrical engineering and computer sciences (EECS).

She previously held positions as an IC Designer with Analog Devices, Wilmington, MA, USA, and as a McKenzie Fellow and a Lecturer of EE with the University of Melbourne, Melbourne, VIC, Australia. She was also the Co-Founder of Cortera Neurotechnologies, Inc., Berkeley, a medical device company founded in 2013 and acquired in 2019, where she held positions as CEO and CTO. She is currently the S. Shankar Sastry Assistant Professor in Emerging Technologies with the EECS Department, University of California at Berkeley. She is also the Co-Director of the Berkeley Wireless Research Center, a Core Member of the Center for Neural Engineering and Prostheses, University of California at Berkeley, and an Investigator with the Chan-Zuckerberg Biohub, San Francisco, CA, USA. Her expertise is in the research and commercialization of implantable medical devices and in developing integrated circuits (ICs) and systems for neurological applications.

Dr. Muller is a member of the technical program committee for IEEE ISSCC, and has previously served on the committees of IEEE CICC and BioCAS. She has also served as a Guest Editor for the IEEE Journal of Solid-State Circuits. She is a Senior Member of the IEEE, and a member of the Solid-State Circuits Society, the Circuits and Systems Society, the Society for Neuroscience, Women in Circuits and Women in Neural Engineering. She has received numerous fellowships and awards, including the National Academy of Engineering Gilbreth Lectureship, the Chan-Zuckerberg Biohub Investigatorship, the Keysight Early Career Professorship, the Hellman Fellowship, and the NSF CAREER Award. She was named one of MIT Technology Review’s top 35 global innovators under the age of 35 (TR35), and one of MedTech Boston’s top 40 healthcare innovators under 40.

Kazuko Nishimura received the B.E. degree in mechanical engineering from Osaka University, Japan, in 1995. In 1995, she joined the Semiconductor Research Center, Panasonic Corporation where she had been engaged in the research and development of high-speed ADCs. Her team developed ultra high-speed ADCs [6] and contributed for a lot of digital read channel applications. From 1998 to 2007, she had joined the task force of optical communication systems, and developed FTTH (Fiber to the home) systems. Her team developed Gbit/s-class CMOS Burst-Mode Optical Transceivers [1][2]. From 2009 to 2012, she had been engaged in the research and development of RF systems. Her team developed Industry's-first LSI that integrated one-seg tuner and demodulation function. From 2006 to 2014, she had been engaged in the research and development of CMOS image sensors and contributed to the mass productions of various cameras, such as DSC, broadcast, surveillance, medical, mobile phone and etc.. And now, she is a Manager in Technology Innovation Division (R&D research division), Panasonic Corporation and has been engaged in the research and management of organic photoconductive film CMOS image sensors and sensor applications [3][4]. She has authored and co-authored 7 international journal papers and conference papers. She holds more than 50 patents.

Esther Rodriguez-Villegasis a Full Professor of Low-Power Electronics at Imperial College, originally known for her engineering techniques to drastically reduce power in integrated circuits.  She subsequently focused her research on life-science applications, founding the Wearable-Technologies-Lab. This lab specialises on both: creating innovative wearable-medical technologies to improve management and diagnosis of chronic diseases; and neural interfaces to facilitate brain research whilst improving animals’ welfare. Esther is also a founder, co-CEO and CSO, of two active life-sciences companies, Acurable and TainiTec. Esther has received many international recognitions and  awards, including two European Research Council grants (2009 and 2016),    a global XPRIZE-award (2014),  and a global AAALAC 3Rs  award for Europe (2018). She was also named the top scientist/engineer in Spain under the age of 36 in 2009 (Complutense award).

Hoi-Jun Yoo is is an IEEE fellow and the ICT Chair professor of School of Electrical Engineering and the director of the System Design Innovation and Application Research Center (SDIA) at KAIST. He is the Chair of Steering Committee of A-SSCC (2020-2024), and was the TPC Chair of ISSCC 2015, and a Plenary Speaker of ISSCC 2019 entitled “Intelligence on Silicon: From Deep Neural Network Accelerators to Brain-Mimicking AI-SoCs”. He has served as a member of the executive committee of ISSCC, Symposium on VLSI, and A-SSCC. He also served as the IEEE SSCS Distinguished Lecturer ('10-'11) and TPC Chairs of International Symposium on Wearable Computers (ISWC) 2010 and A-SSCC 2008. He was a guest editor of IEEE JSSC and IEEE T-BioCAS, and is an associate editor of IEEE JSSC and SSCL.

His current research interests are Bio Inspired AI Chip Design, Multicore AI-SoC design including DNN accelerators, Network on a Chip, and high speed and low power memory. He has published more than 250 papers, and wrote or edited 5 books “DRAM Design”(1997, Hongneung). “High Performance DRAM”(1999 Hongneung), “Low Power NoC for High Performance SoC Design”(2008, CRC), “Mobile 3D Graphics SoC”(2010, Wiley), and “BioMedical CMOS ICs”(Co-editing with Chris Van Hoof, 2010, Springer), and many chapters of books.

Dr. Yoo received the Order of Service Merit from Korean President in 2011 for his contribution to Korean memory industry, the Scientist/Engineer of the month Award from Ministry of Education, Science and Technology of Korea in 2010, Kyung-Am Scholar Award in 2014. He also received the Electronic Industrial Association of Korea Award for his contribution to DRAM technology in 1994, Hynix Development Award in 1995, the Korea Semiconductor Industry Association Award in 2002, Best Research of KAIST Award in 2007, Excellent Scholar of KAIST Award in 2011, Best Scholar of KAIST Award in 2019, and was a co-recipient of ASP-DAC Design Award in 2001, A-SSCC Outstanding Design Awards in 2005, 2006, 2007, 2010, 2011, 2014, ISSCC/DAC Student Design Contest Awards in 2007, 2008, 2010, 2011, and ISSCC Demonstration Session Recognitions in 2016, 2017, 2019, 2020, and Best Paper Award of IEEE AI-CAS in 2019.

Danielle Griffith received the B.S.E.E. and M.Eng. degrees from the Massachusetts Institute of Technology, Cambridge in 1996 and 1997, respectively. She joined Motorola in Tempe, AZ in 1997 and worked in the area of RF circuit design.  In 2003, she joined Texas Instruments in Dallas, Texas and is a Fellow in the Connectivity business unit.  She develops circuits and techniques for reducing cost, power consumption, and circuit board area for low power wireless connectivity products.  Her current focus areas are architectures for efficient wireless systems, low power oscillators and MEMS circuitry.  She has published >50 papers, most of them in IEEE journals or conferences.   She has written a book chapter titled “Synchronization Clocks for Ultra-Low Power Wireless Networks” which was published by Springer as a part of the book “Ultra-Low-Power Short-Range Radios”.  Danielle holds 19 issued US patents and has given multiple university and IEEE conference tutorial and workshop sessions.  She was a member of the Technical Program Committees for the IEEE RFIC Symposium for conferences years 2014 and 2015, the IEEE International Solid-State Circuits Conference for conference years 2015-2019, and the VLSI Symposium starting in 2019. 

Chulwoo Kim received the B.S. and M.S. degrees in electronics engineering from the Korea University in 1994 and 1996, respectively, and the Ph.D. degree in electrical and computer engineering from the University of Illinois at Urbana-Champaign in 2001.

In 1999, he worked as a summer intern at the Design Technology at Intel Corporation, Santa Clara, CA. In May 2001, he joined IBM Microelectronics Division, Austin, TX, where he was involved in Cell processor design. Since September 2002, he has been with the School of Electrical Engineering, Korea University, where he is currently a Professor. He was a Visiting Professor at the University of California at Los Angeles in 2008 and at the University of California at Santa Cruz in 2012. He is a coauthor of two books, namely, CMOS Digital Integrated Circuits: Analysis and Design (McGraw Hill, 4th edition 2014) and High-Bandwidth Memory Interface (Springer, 2013). His current research interests are in the areas of wireline transceiver, memory, power management and data converters.

Dr. Kim received the Samsung HumanTech Thesis Contest Bronze Award (1996), the ISLPED Low-Power Design Contest Award (2001, 2014), the DAC Student Design Contest Award (2002), SRC Inventor Recognition Awards (2002), the Young Scientist Award from the Ministry of Science and Technology of Korea (2003), the Seoktop Award for excellence in teaching (2006, 2011) and ASP-DAC Best Design Award (2008) and Special Feature Award (2014), Korea Semiconductor Design Contest: Prime Minister Award (2016). He served on the Technical Program Committee of the IEEE International Solid-State Circuits Conference and as a Guest Editor for IEEE Journal of Solid-State Circuits. He is currently on the editorial board of IEEE Transactions on VLSI Systems and the Chair of the SSCS Seoul Chapter. He has been elected as Distinguished Lecturer of the IEEE Solid-State Circuits Society for 2015–2016.

 

Frank O'Mahony leads the I/O Circuit Technology group within Advanced Design at Intel in Hillsboro, Oregon, where he is a Senior Principal Engineer. His team coordinates circuit-process co-design for wireline I/O at Intel. They also design and test the first I/Os on each new CMOS process technology. From 2003 until 2011 he was a member of the Signaling Research group in Intel’s Circuit Research Lab. His past work includes high-speed and low-power transceivers, clock generation and distribution, equalization, analog circuit scaling, and on-die measurement techniques. Frank received the BS, MS, and PhD degrees in electrical engineering from Stanford University. Frank has been on the ISSCC Technical Program Committee since 2012 including five years as the Wireline Subcommittee chair. He currently serves as the ISSCC Forums Chair. Since 2003 he has published over 40 papers in peer-reviewed conferences and journals on the topic of wireline transceivers and clocking. He has received the ISSCC Jack Kilby Award, IEEE Journal on Solid-State Circuits Best Paper Award and TCAS Darlington Best Paper Award. He is a Senior Member of the IEEE and served as an IEEE Distinguished Lecturer.

Yusuke Oike received the B.E., M.E., and Ph.D. degrees in electronic engineering from the University of Tokyo, Tokyo, Japan, in 2000, 2002 and 2005, respectively. In 2005, he joined Sony Corporation, Tokyo, Japan, where he was involved in research and development of architectures, circuits, and devices for image sensors. From 2010 to 2011, he was a visiting scholar at Stanford University, CA. Currently, he is in charge of research and development of CMOS image sensors as Deputy Senior General Manager of Sony Semiconductor Solutions, Japan. He is appointed as Distinguished Engineer of Sony Corporation. He is also a director of Sony Advanced Visual Sensing AG at Zurich. His current research interests include pixel architecture, mixed-signal circuit design for image sensors, and image processing algorithms.

He has published more than 50 technical publications, including 8 ISSCC, 5 VLSI Symposium, and 3 IEDM papers. He has given several invited talks, including ISSCC Forum in 2018 and 2021, and IEDM Tutorial in 2020. He is a senior member of IEEE. He has served technical program committees of international conferences, including ISSCC IMMD sub-committee member for ISSCC 2012-2016, VLSI Circuits Symposium committee member for VLSI 2016-2019, and VLSI Circuits Symposium Program Chair for VLSI 2020 and 2021.

Farhana Sheikh (IEEE SM’14, IEEE M’93) received the B.Eng. degree in Systems and Computer Engineering with high distinction, also receiving Chancellor’s Medal, from Carleton University, Ottawa, Canada, in 1993 and the M.Sc. and Ph.D. degrees in Electrical Engineering and Computer Sciences from the University of California, Berkeley, in 1996 and 2008, respectively. In 1993, Farhana was selected as one of 100 Canadians to Watch in Canada’s national magazine, Macleans.  From 1993 to 1994 she worked at Nortel Networks as a software engineer in firmware and embedded system design. From 1996 to 2001, she was at Cadabra Design Automation, now part of Synopsys as software engineer and senior manager.  She joined Intel Corporation after her Ph.D. in 2008 where she worked as a Senior Research Scientist and Staff Scientist in the Circuit Research Lab, part of Intel Labs from 2008 to 2014.  In 2014, she became Senior Staff Scientist and Technical Manager of Digital Communications Lab, in Wireless Communications Research, Intel Labs and led a team of researchers in the area of digital communications and signal processing architectures and circuits. In October 2016, after her Intel sabbatical, she joined Radio Circuits Technology Lab as a senior staff scientist, working on next generation digital radio circuits.  Her research interests include low-power digital and mixed-signal CMOS design, energy-efficient high-performance circuits next generation wireless systems, wireless security, cryptography, and signal/image processing. Farhana has co-authored over 30 publications in VLSI circuit design, including editing and co-authoring chapters in a book on security titled Circuits and Systems for Security and Privacy. Farhana has filed over 15 patents on circuits and systems for wireless communication, cryptography circuits, and 3-D graphics circuits at Intel Corporation.  Dr. Sheikh was a recipient of the Association of Professional Engineers of Ontario Gold Medal for Academic Achievement, the NSERC’67 scholarship for graduate studies, and the Intel Foundation Ph.D. Fellowship. In 2012, she received the ISSCC Distinguished Technical Paper award.