JSSC Best Paper Award
The JSSC Best Paper Award is awarded every year. For more information regarding this award, please contact, JSSC Editor-in-Chief, Jan Craninckx. The JSSC Best Paper Award winners will be announced at ISSCC.
Best Paper of 2016:
A 2.2 GHz Continuous-Time ΔΣ ADC With −102 dBc THD and 25 MHz Bandwidth
The JSSC 2016 Best Paper was awarded for "A 2.2 GHz Continuous-Time ΔΣ ADC With −102 dBc THD and 25 MHz Bandwidth". It was published in the December 2016 issue of the IEEE Journal of Solid-State Circuits, Vol. 51, No. 12, pp. 2906-2916. Read this paper in full on IEEE Xplore by clickinghere. The authors of the paper are: Lucien Breems, Muhammed Bolatkale, Hans Brekelmans, Shagun Bajoria, Jan Niehof, Robert Rutten, Bert Oude-Essink, Franco Fritschij, Jagdip Singh, Gerard Lassache.
Shagun Bajoria accepted the 2017 JSSC Best Paper Award on behalf of fellow authors at ISSCC 2018. SSCS President Bram Nauta presented the award.
Past JSSC Best Paper Award Winners
Tzu-Chien Hsueh, Frank O'Mahony, Mozghan Mansuri, Bryan Casper
Vol. 50, No. 7, pp. 1711-1721
Michael Boers, Bagher Afshar, Iason Vassiliou, Saikat Sarkar, Sean T. Nicolson, Ehsan Adabi, Bevin George Perumana, Theodoros Chalvatzis, Spyros Kavvadias, Padmanava Sen, Wei Liat Chan, Alvin Hsing-Ting Yu, Ali Parsa, Med Nariman, Seunghwan Yoon, Alfred Grau Besoli, Chryssoula A. Kyriazidou, Gerasimos Zochios, Jesus A. Castaneda, Tirdad Sowlati, Maryam Rofougaran, and Ahmadreza Rofougaran.
Vol. 49, No. 12, pp. 3031-3045
Ron Kapusta, Junhua Shen, Steven Decker, Hongxing Li, Eitake Ibaragi, Haiyang Zhu
"A 14b 80 MS/s SAR ADC With 73.6 dB SNDR in 65 mm CMOS"
Vol. 48, No. 12, pp. 3059-3066, Dec. 2013
David Murphy, Hooman Darabi, Asad Abidi, Amr Amin Hafez, Ahmad Mirzael, Mohyee Mikhemar, and Mau-Chung Frank Chang
"A Blocker-Tolerant, Noise-Cancelling Receiver Suitable for Wideband Wireless Applications"
Vol. 47, No. 12, pp. 2943-2963, Dec. 2012
Muhammed Bolatkale, Lucien J. Breems, Robert Rutten and Kofi A. A. Makinwa
"A 4-GHz Continuous-Time Δ-ΣADC with 70-dB DR and -74 dBFS THD in 125-MHz BW"
Vol. 46, no. 12, pp. 2857-2868, Dec. 2011.
Christopher Peter Hurrell, Colin Lyden, David Laing, Derek Hummerston, and Mark Vickery
"An 18 b 12.5 MS/s ADC With 93 dB SNR,"
Vol. 45, no. 12, pp. 2647-2654, Dec. 2010.
Byungsub Kim, Yong Liu, Timothy O. Dickson, John F. Bulzacchelli and Daniel J. Friedman
A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS
Volume 44, No. 12, pp. 3526-3538 in December 2009.
Junghwan Han and Ranjit Gharpurey
Recursive Receiver Down-Converters With Multiband Feedback and Gain-Reuse
Volume 43, Issue 5, May 2008 Pages: 1119 - 1131
John Poulton, Robert Palmer, Andrew Fuller, Trey Greer, John Eyles, William Dally and Mark Horowitz
A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS
Volume: 42, Issue: 12, December 2007, Pages:2745 - 2757
Jonathan B. Ashbrook, Hyeon-Min Bae, Sanjiv Chopra, Jinki Park, Naresh R. Shanbhag and Andrew C. Singer
An MLSE Receiver for Electronic Dispersion Compensation of OC-192 Fiber Links Digital
Volume: 41, Issue: 11, November 2006, Pages:2541-2554
Drs. Michiel. A. P. Pertijs, Kofi A. A. Makinwa and Johan H. Huijsing
A CMOS smart temperature sensor with a 3s inaccuracy of + 0.1° C from -55° C to 125° C
Volume: 40, Issue: 12, December 2005, Pages:2805 - 2815
Xiang Guan, Hossein Hashemi and Ali Hajimiri
A Fully Integrated 24-GHz Eight-Element Phased-Array Receiver in Silicon
Volume: 39 , Issue: 12, December 2004, Pages:2311 - 2320
Manstretta, Danilo.; Brandolini, Massimo.; Svelto, Francesco
Second-order intermodulation mechanisms in CMOS downconverters
Volume: 38 , Issue: 3, March 2003, Pages:394- 406
Alireza Shirvani, David K. Su and Bruce A. Wooley
A CMOS RF power amplifier with parallel amplification for efficient power control
Volume: 37 , Issue: 6 , June 2002, Pages:684 - 693
Marko Sokolich, Charles H.Fields, Stephen Thomas III, Binqiang Shi, Young Kim Boegeman, Mary Montes, Rosanna Martinez, Allan R. Kramer, and Meena Madhav
A low-power 72.8-GHz Static Frequency Divider in AlInAs/InGaAs HBT Technology
vol. 36, pp. 1328 - 1333, September 2001
Ichiro Fujimori, Akihiko Nogi, and Tetsuro Sugimoto
A Multibit Delta–Sigma Audio DAC with 120-dB Dynamic Range
vol. 35, pp. 1066 - 1073, August 2000.
Brian P. Brandt and Joseph Lutsky
A 75-mW, 10-b, 20-MSPS CMOS Subranging ADC with 9.5 Effective Bits at Nyquist
vol. 34, pp. 1788 - 1795, December 1999.
Mark. J. Loinaz, K. J. Singh, Andrew. J. Blanksby, David A. Inglis, Kamran. Azadet, and Brain Ackland
A 200-mW, 3.3-V, CMOS Color Camera IC Producing 352 × 288 24-b Video at 30 Frames/s
vol. 33, pp. 2092 - 2103, December 1998.
Todd L. Brooks, David H. Robertson, Daniel F. Kelly, Anthony Del Muro, and Stephen W. Harston
A cascaded sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR
vol. 32, pp. 1896 - 1906, December 1997.
Takanori Saeki, Yuji Nakaoka, Mamoru Fujita, Akihito Tanaka, Kyoichi Nagata, Kenichi Sakakibara, Tatsuya Matano, Yukio Hoshino, Kazutaka Miyano, Satoshi Isa, Shigeyuki Nakazawa, Eiichiro Kakehashi, John M. Drynan, MasahirKomuro, Tadashi Fukase, Haruo Iwasaki, Motohiro Takenaka, Junichi Sekine, Masahiko Igeta, Nobuko Nakanishi, Toshiro Itani, Kazuyoshi Yoshida, Hiroshi Yoshino, Syuichi Hashimoto, Tsuyoshi Yoshii, Michihiko Ichinose, Tomoo Imura, Masato Uziie, Shinichi Kikuchi, Kuniaki Koyama, Yukio Fukuzo, and Takashi Okuda
A 2.5-ns Clock Access, 250-MHz, 256-Mb SDRAM with Synchronous Mirror Delay
vol. 31, pp. 1656- 1668, November 1996
Loke Kun Tan and Henry Samueli
A 200 Mhz Quadrature Digital Synthesizer/Mixer in 0.8 mm C.M.O.S.
vol. 30, pp. 193-200, March 1995
Michiel de Wit. Khen-San Tan. and Richard K. Hester
A Low-Power 12b Analog-to-Digital Converter with On-Chip Precision Trimming
vol. 28, pp. 455 - 461, April 1993
Masato Motomura, Hachiro Yamada, Tadayoshi Enomoto
A 2K-Word Dictionary Search Processor (DISP) LSI with an Approximate Word Search Capability
vol. 27, pp. 883 - 891, June 1992