JSSC Best Paper Award

IEEE Journal of Solid-State Circuits Best Paper Award Through the Years

Each year, the IEEE Journal of Solid-State Circuits Best Paper Award is presented to the authors of a paper tat is considered by the journal's editorial staff and reviewers to be the most exceptional paper published in the preceding full-year volume. The award is based on accuracy, originality, technical content, and the quality of the article. The award is presented each year at the International Solid-State Circuits Conference

 

2014

Michael Boers, Bagher Afshar, Iason Vassiliou, Saikat Sarkar, Sean T. Nicolson, Ehsan Adabi, Bevin George Perumana, Theodoros Chalvatzis, Spyros Kavvadias, Padmanava Sen, Wei Liat Chan, Alvin Hsing-Ting Yu, Ali Parsa, Med Nariman, Seunghwan Yoon, Alfred Grau Besoli, Chryssoula A. Kyriazidou, Gerasimos Zochios, Jesus A. Castaneda, Tirdad Sowlati, Maryam Rofougaran, and Ahmadreza Rofougaran. 

A 16TX/16RX 60 GHz 802.11ad Chipset With Single Coaxial Interface and Polarization Diversity

Vol. 49, Issue. 12, pp. 3031-3045, Dec 2014

2013

Ron Kapusta, Junhua Shen, Steven Decker, Hongxing Li, Eitake Ibaragi, Haiyang Zhu
"A 14b 80 MS/s SAR ADC With 73.6 dB SNDR in 65 mm CMOS"
Vol. 48, Issue 12, pp. 3059-3066, Dec. 2013

2012

David Murphy, Hooman Darabi, Asad Abidi, Amr Amin Hafez, Ahmad Mirzael, Mohyee Mikhemar, and Mau-Chung Frank Chang 
"A Blocker-Tolerant, Noise-Cancelling Receiver Suitable for Wideband Wireless Applications"
Vol. 47, Issue 12, pp. 2943-2963, Dec. 2012

 

2011

Muhammed Bolatkale, Lucien J. Breems, Robert Rutten and Kofi A. A. Makinwa
"A 4-GHz Continuous-Time Δ-ΣADC with 70-dB DR and -74 dBFS THD in 125-MHz BW"
Vol. 46, Issue 12, pp. 2857-2868, Dec. 2011.

2010

Christopher Peter Hurrell, Colin Lyden, David Laing, Derek Hummerston, and Mark Vickery
"An 18 b 12.5 MS/s ADC With 93 dB SNR,"
Vol. 45, Issue 12, pp. 2647-2654, Dec. 2010. 

2009

Byungsub Kim, Yong Liu, Timothy O. Dickson, John F. Bulzacchelli and Daniel J. Friedman
A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS
Volume 44, Issue 12, pp. 3526-3538 in December 2009.

2008

Junghwan Han and Ranjit Gharpurey
Recursive Receiver Down-Converters With Multiband Feedback and Gain-Reuse
Volume 43, Issue 5, pp. 1119 – 1131, May 2008

2007

John Poulton, Robert Palmer, Andrew Fuller, Trey Greer, John Eyles, William Dally and Mark Horowitz
A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS
Volume: 42, Issue: 12, pp. 2745 – 2757, December 2007

2006

Jonathan B. Ashbrook, Hyeon-Min Bae, Sanjiv Chopra, Jinki Park, Naresh R. Shanbhag and Andrew C. Singer
An MLSE Receiver for Electronic Dispersion Compensation of OC-192 Fiber Links Digital
 
Volume: 41, Issue: 11, pp. 2541-2554, November 2006

2005

Drs. Michiel. A. P. Pertijs, Kofi A. A. Makinwa and Johan H. Huijsing
A CMOS smart temperature sensor with a 3s inaccuracy of + 0.1° C from -55° C to 125° C
Volume: 40, Issue: 12, pp. 2805 – 2815, December 2005

2004

Xiang Guan, Hossein Hashemi and Ali Hajimiri
A Fully Integrated 24-GHz Eight-Element Phased-Array Receiver in Silicon
Volume: 39 , Issue: 12, pp. 2311 – 2320, December 2004

2003

Manstretta, Danilo.; Brandolini, Massimo.; Svelto, Francesco
Second-order intermodulation mechanisms in CMOS downconverters
Volume: 38 , Issue: 3, pps.394- 406, March 2003

2002

Alireza Shirvani, David K. Su and Bruce A. Wooley
A CMOS RF power amplifier with parallel amplification for efficient power control
Volume: 37 , Issue: 6 , pps.684 – 693, June 2002

2001

Marko Sokolich, Charles H.Fields, Stephen Thomas III, Binqiang Shi, Young Kim Boegeman, Mary Montes, Rosanna Martinez, Allan R. Kramer, and Meena Madhav
A low-power 72.8-GHz Static Frequency Divider in AlInAs/InGaAs HBT Technology 
vol. 36, pp. 1328 - 1333, September 2001

2000

Ichiro Fujimori, Akihiko Nogi, and Tetsuro Sugimoto
A Multibit Delta–Sigma Audio DAC with 120-dB Dynamic Range
vol. 35, Issue 9, pp. 1066 - 1073, August 2000.

1999

Brian P. Brandt and Joseph Lutsky
A 75-mW, 10-b, 20-MSPS CMOS Subranging ADC with 9.5 Effective Bits at Nyquist

vol. 34, Issue 12, pp. 1788 - 1795, December 1999.

1998

Mark. J. Loinaz, K. J. Singh, Andrew. J. Blanksby, David A. Inglis, Kamran. Azadet, and Brain Ackland 
A 200-mW, 3.3-V, CMOS Color Camera IC Producing 352 × 288 24-b Video at 30 Frames/s 
vol. 33, Issue 12, pp. 2092 - 2103, December 1998.

1997

Todd L. Brooks, David H. Robertson, Daniel F. Kelly, Anthony Del Muro, and Stephen W. Harston
A cascaded sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR 
vol. 32, Issue 12, pp. 1896 - 1906, December 1997.

1996

Takanori Saeki, Yuji Nakaoka, Mamoru Fujita, Akihito Tanaka, Kyoichi Nagata, Kenichi Sakakibara, Tatsuya Matano, Yukio Hoshino, Kazutaka Miyano, Satoshi Isa, Shigeyuki Nakazawa, Eiichiro Kakehashi, John M. Drynan, MasahirKomuro, Tadashi Fukase, Haruo Iwasaki, Motohiro Takenaka, Junichi Sekine, Masahiko Igeta, Nobuko Nakanishi, Toshiro Itani, Kazuyoshi Yoshida, Hiroshi Yoshino, Syuichi Hashimoto, Tsuyoshi Yoshii, Michihiko Ichinose, Tomoo Imura, Masato Uziie, Shinichi Kikuchi, Kuniaki Koyama, Yukio Fukuzo, and Takashi Okuda
A 2.5-ns Clock Access, 250-MHz, 256-Mb SDRAM with Synchronous Mirror Delay
vol. 31, Issue 11, pp. 1656- 1668, November 1996

1995

Loke Kun Tan and Henry Samueli 
A 200 Mhz Quadrature Digital Synthesizer/Mixer in 0.8 mm C.M.O.S.
vol. 30, Issue 3, pp. 193-200, March 1995

1994 - N/A

1993

Michiel de Wit. Khen-San Tan. and Richard K. Hester 
A Low-Power 12b Analog-to-Digital Converter with On-Chip Precision Trimming
vol. 28, Issue 4, pp. 455 - 461, April 1993

1992

Masato Motomura, Hachiro Yamada, Tadayoshi Enomoto 
A 2K-Word Dictionary Search Processor (DISP) LSI with an Approximate Word Search Capability 
vol. 27, Issue 6, pp. 883 - 891, June 1992

 

1991

Yuh-Min Lin, Beomsup Kim, Paul R. Gray

A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3-μm CMOS

Vol. 26, Issue 4, pp 628-636, April 1991

 

1990

Howard L. Kalter, Charles H. Stapper, John E. Barth, Jr., John Dilorenzo, Charles E. Drake, John A Fifield, Gordon A Kelley, Jr., Scott C. Lewis, Willem  B. van der Hoeven, and James A Yankosky

A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC

Vol. 25, Issue 5, pp. 1118-1128, October 1990

 

 

1989

Jiren  Yuan  and  Christer  Svensson  

High-Speed  CMOS  Circuit Technique

Vol. 24, Issue 1, pp. 62-70, February 1989

 

1988

Ken Poulton, John J. Corcoran, and Thomas Hornak

A  1-GHz 6-bit ADC System

Vol. 22, Issue 6, pp. 962-970, December 1987

 

1987

Stephen T. Flannagan, Paul A. Reed, Peter H. Voss, Scott G. Nogle, Lawrence J. Day, David Y. Sheng, John J. Barnes, and Roger I. Kung

Two 13-ns 64K CMOS SRAM's with Very Low Active Power and Improved Asynchronous Circuit Techniques

Vol 21, Issue 5, pp. 692-703, October 1986

 

1986/1985

Yukio Akazawa, Noboru Ishihara, Tsutomu Wakimoto, Kuniyasu Kawarada, and Shinsuke Konaka

A Design and Packaging Technique for a High-Gain, Gigahertz­ Band Single-Chip Amplifier

Vol 21, Issue 3, pp. 417-423, June 1986

 

1984

Raymond Pinkham, Donald J. Redwine, Fred  A.  Valente,  Troy H. Herndon, and Daniel F. Anderson

A High Speed Dual Port Memory with Simultaneous Serial and Random Mode Access  for Video Applications

 

Vol. 19, Issue 6, pp. 999-1007, December 1984